Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Preemphasis and equalizer in the SerDes design

Status
Not open for further replies.

raymond_luo2003

Member level 1
Joined
May 20, 2004
Messages
41
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
464
serdes pre-emphasis equalizer

Dear all,

I am working on the high speed SerDes design. I got some papers which mention about using the pre-emphasis and post-equalizer to improve the eyediagram at receiver side which is attenuated by cable loss.

Altough that makes sense to use those types of techique, I feel it is quite challenging to implement it.
a) Usually we require the one original serialized data stream and one (or more than one, depends the FIR structure) very short precised delayed serialized data stream with coefficient a to bulid FIR. I just wonder how to implement the precise delay line under PVT variation?

b) Another methodology is to delay parallel data before the serializer which let us use the low frequency clock for easy implementation. The issue of this is we have to duplicate an entire serializer only for generatiing the delayed serialzed data stream. It is big area and power copnsumption!


Anyone got relevant rexperience would help me a lot!!

Thanks
Raymond
 

equalizer serdes

use filter as delay element, the delay can be controlled by PLL or DLL
 

use transmission line as delay element, but the area is large
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top