Which case can generate lower phase noise in band ?

(1) fcmp=25MHz, fvco=800MHz, Ndiv=32, LoopBW=100kHz
fout=100MHz

(2) fcmp=25MHz, fvco=3200MHz, Ndiv=128, LoopBW=100kHz
fout=100MHz

I want to get 100MHz signal for both cases.
I assume integer-N PLL synthesizer.
Which case can generate lower in-band phase noise regarding fout=100MHz ?

depends on the vco phase noise vs offset frequency, which you conveniently left off. you also left out the phase noise of your 25 MHz reference source, and what type of logic you are using for the divider.
In general, if you know what you are doing, the 800 MHz vco approach should be better.
you should instead use a 100 MHz crystal oscillator and lock it to 25 MHz if possible.

I would expect the phase noise of an open loop VCO at 800 MHz to be about 6dB better than a similar open loop VCO at 3200 MHz.

The difference in rates of 20*LOG(128)=42dB vs 20*LOG(30)=30dB it will improve phase noise by 12dB (42dB vs 30dB).

So might be possible the overall phase noise of the 3200 MHz PLL to be 6dB better than 800 MHz PLL.

Thanks for answering.

biff44 said:

In general, if you know what you are doing, the 800 MHz vco approach should be better.

Click to expand...

vfone said:

So might be possible the overall phase noise of the 3200 MHz PLL to be 6dB better than 800 MHz PLL.

Click to expand...

Uuum, different opinions between biff44 and vfone.

My opinion is that both 800MHz and 3200MHz PLL give same in-band phase noise regarding fout=100MHz if PLL synthesizer is Integer-N.
However I expect 3200MHz PLL show better in-band phase noise if PLL synthesizer is Fractional-N.
And 3200MHz PLL has advantage about occupied area for loop filter, if charge pump current value is same.

====================================================
Lpll=Ndiv^2 * Lref
Lout=Lpll / Nout^2=(Ndiv/Nout)^2 * Lref

Lpll : in-band phase noise of PLL
Lref : in-band phase noise of reference clock, feedback divider and PFD.
Lout : in-band phase noise of fout=100MHz

(1) Ndiv=32, Nout=8, Ndiv/Nout=4
(2) Ndiv=128, Nout=32, Ndiv/Nout=4

Mixer Phase Noise is always multiplied by your divider ratio.

SO use the lowest possible phase noise reference (OCXO) for testing and the lowest divider.
For design , lowest phase noise VCO and lowest divider N value.

But in your case the mixer frequency is already chosen at 25MHz , so it may not matter in theory with two loops. ... not sure.
because phase noise reduces after divider N at mixer f then multiplies by N to VCO.

800 MHz solution will be less noisy because ;

-Kvco will be smaller ( less sensitivity )
-Divider stages will be less so additive noise coming from dividers will also be less.

BigBoss said:

800 MHz solution will be less noisy

Click to expand...

I also think so.
However it is very small difference.
So in-band phase noises are almost same between (1) and (2) regarding fout=100MHz.

BigBoss said:

because ;
-Kvco will be smaller ( less sensitivity )

Click to expand...

I don't think that large Kvco degrade in-band phase noise as far as we have large loop-gain.
Of course, Large Kvco will degrade out-band phase noise.

BigBoss said:

-Divider stages will be less so additive noise coming from dividers will also be less.

Click to expand...

I also think so.
However Its effect is relative small.

I am not following what Vfone is saying. yes 20 log 128 is bigger than 20 Log 30. but these are control loop LOSSES, not gains. You have a certain open loop gain in your control loop that is Gtot = Gosc * Gainloopamp /Divider ratio. a big divider ratio drops the open loop gain, so it would have 12 dB worse phase noise, all things being equal

f(t) = cos(ωt + θ)
Frequency division by N divides the cosine function argument (ωt + θ) by N.
Consequently any Phase Noise term in the θ is also divided by N, so the Phase Noise is decreased by 20*LOG(N) dB.
Higher the oscillator divider N, lower the Phase Noise at the output of the divider (or input of the Phase Detector).

vfone said:

f(t) = cos(ωt + θ)
Frequency division by N divides the cosine function argument (ωt + θ) by N.
Consequently any Phase Noise term in the θ is also divided by N, so the Phase Noise is decreased by 20*LOG(N) dB.
Higher the oscillator divider N, lower the Phase Noise at the output of the divider (or input of the Phase Detector).

Click to expand...

Oh I see what you did. we are talking about different things.
A PLL at 3 GHz in general has worse phase noise than one at 800 MHz, and it is typically so much worse that when you divide 3 Ghz by 4 to get to around 800 MHz, the straight 800 MHz pll is better.

So you would somehow need the 3 GHz phase locked oscillator to start off 12 dB better in phase noise than the 800 MHz phase locked oscillator, THEN the 3000 MHz oscillator has a better chance of having lower phase noise when divided all the way down.

biff44 said:

So you would somehow need the 3 GHz phase locked oscillator to start off 12 dB better in phase noise than the 800 MHz phase locked oscillator, THEN the 3000 MHz oscillator has a better chance of having lower phase noise when divided all the way down.

Click to expand...

I don't think 3200MHz PLL can give better in-band phase noise than 800MHz PLL as far as integer-N PLL amd same 25MHz reference phase noise.

Again see equations I appended.

pancho_hideboo said:

Lpll=Ndiv^2 * Lref
Lout=Lpll / Nout^2=(Ndiv/Nout)^2 * Lref

Lpll : in-band phase noise of PLL
Lref : in-band phase noise of reference clock, feedback divider and PFD.
Lout : in-band phase noise of fout=100MHz

(1) Ndiv=32, Nout=8, Ndiv/Nout=4
(2) Ndiv=128, Nout=32, Ndiv/Nout=4

Click to expand...

Still I wait for useful opinion or insight.

Some product tranceiver ICs, e.g. TI-CC1120 and SiliconLabs-Si4461, can give very excellent low in-band phase noise for 100MHz ~ 900MHz from 4000MHz-PLL.
This is a originate of my question.