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VHDL - Clock divider

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omerysmi

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if for example i have 50Mhz clock and i want to divide it by 5, how could it be possible?
each rising/falling edge divide my clock in 2 right? so how much rising/falling edges i need to divide it by 5?
 

What's the waveform you want to generate and where is it used for?

People avoid generated clocks in FPGA design and use clock enable signals wherever possible.
 

Deviating from the clock tree can lead to timing problems.

I would do as FvM suggests.

Code VHDL - [expand]
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count : process(clock)
begin
  if rising_edge(clock) then
    count <= count + 1;
    enable_pulse <= '0';
    if count = 5 then
      enable_pulse <= '1';
      count <= 1;
    end if;
  end if;
end process;
 
some_other : process (clock) is
 
begin
 
  -- if rising_edge(clock) and enable_pulse='1' then -- google gated clock
  if rising_edge(clock) then
    if enable_pulse='1' then
...
end process;
 

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