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sine wave phase shifting to 180 vhdl

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preethi19

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hi all i have managed to generate a sin wave using the lut. I am designing a BPSK modulator. I need to phase shift this sin wave to 180 degree for the mux. I wrote another lut for sin wave 180 degree and it works fine but is der any better way to do this.. Found online wer they told to delay the sin wave for certain period and it resulting in 180 phase shift. So how exactly am i supposed to delay my sin wave from the lut... If there are any other ways kindly let me know in vhdl!!! thank you!!!
 

A digital delay line (a.k.a. a shift register) would do that, or in Xilinx there is the SRL primitive you can use to create a shift register that you can set to a constant 1-16/32 shifts.
 

preethi19 said:
hi all i have managed to generate a sin wave using the lut. I am designing a BPSK modulator. I need to phase shift this sin wave to 180 degree for the mux. I wrote another lut for sin wave 180 degree and it works fine but is der any better way to do this.. Found online wer they told to delay the sin wave for certain period and it resulting in 180 phase shift. So how exactly am i supposed to delay my sin wave from the lut... If there are any other ways kindly let me know in vhdl!!! thank you!!!
Click to expand...

you can read your first lut in reverse ....
you can implement dual port rom for that,,,
 

hi thank you for the reply... i can build a parellel in parallel out shift reg... thing is i just write the simple logic as for every rising edge the input goes to output which will cause a delay.... but like many clock cycles are required to generate one full sine wave from the lut... So i need to delay the sine wave(180) atleast to half the period of the first sine wave (0)... This requires so many clock cycle delays... could you pls tell me on how to do that...

- - - Updated - - -

this is my sine wave code... i have mentioned sin2 to be the phase shifted wave but dont know how to bring the logic for that one... could you pls let me know how to write it in vhdl code the delay logic for sin2

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity askmod is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           accuEn : in STD_LOGIC;
           accu_in : in std_logic_vector (4 downto 0);
           sin1 : inout STD_LOGIC_VECTOR (7 downto 0);
           sin2 : out STD_LOGIC_VECTOR (7 downto 0)
           );
end askmod;
 
architecture Behavioral of askmod is
 
signal accu_out : std_logic_vector (4 downto 0);
signal address : std_logic_vector (2 downto 0);
 
begin
 
process (rst, clk)  % accumulator/address generator
 
-- note that we can have a bit vector for a variable
variable accu_v : STD_LOGIC_VECTOR (4 downto 0);
 
begin
 
-- async reset
if rst = '1' then
 
-- initialize the output and the variable to "0..."
accu_out <= (others=>'0'); 
address <= (others=>'0'); 
accu_v := (others=>'0'); 
 
elsif clk'event and clk = '1' then
if accuEn = '1' then
 
accu_v := accu_v + accu_in;
 
end if;
end if;
accu_out <= accu_v;
address (2 downto 0) <= accu_v (4 downto 2);  
end process;
 
process(clk, rst, address)  %lut 
begin
 
if rst = '1' then
sin1 <= "00000000";
sin2 <= "00000000";
 
elsif(clk'event and clk='1') then 
case (address) is
when "000" => sin1 <= "10000000";
when "001" => sin1 <= "11011010";
when "010" => sin1 <= "11111111";
when "011" => sin1 <= "11011010";
when "100" => sin1 <= "10000000";
when "101" => sin1 <= "00100110";
when "110" => sin1 <= "00000001";
when "111" => sin1 <= "00100110";
when others => sin1 <= "00000000";
 
end case;
end if;
 
end process;
 
end Behavioral;
 
Last edited by a moderator:

180 degrees phase shift is just a sign change.
For BPSK you don't need both sine waves at the same time, and then there is an even better solution, without a mux.
You can do the phase shift by adding/subtracting to the phase accumulator or the address. 180 degrees is probably the simplest case, just invert one bit: address(2).

You should not mix numeric_std with the non-standard std_logic_*** libraries. You have no conflict because it seems that you use nothing from numeric_std.
My recommendation is to use only numeric_std. You should then change from "std_logic_vector" to "unsigned" for the signals you are using with arithmetic operations.
 

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