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Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 always @(posedge clk) begin case (nibble) 4'b0000 : num_1s <= 3'd0; 4'b0001 : num_1s <= 3'd1; 4'b0010 : num_1s <= 3'd1; 4'b0011 : num_1s <= 3'd2; 4'b0100 : num_1s <= 3'd1; 4'b0101 : num_1s <= 3'd2; 4'b0110 : num_1s <= 3'd2; 4'b0111 : num_1s <= 3'd3; 4'b1000 : num_1s <= 3'd1; 4'b1001 : num_1s <= 3'd2; 4'b1010 : num_1s <= 3'd1; 4'b1011 : num_1s <= 3'd3; 4'b1100 : num_1s <= 3'd2; 4'b1101 : num_1s <= 3'd3; 4'b1110 : num_1s <= 3'd3; 4'b1111 : num_1s <= 3'd4; endcase accum <= init_accum ? 0 : (accum + num_1s); end
How to count no of ones in a data stream of 4 bits
What is up with all the vague questions lately that require clarification?