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What parameter decides setup & hold time of flop?

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aanudhonde

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Hello all,
Suppose I am having a D flip flop.
Now what are the parameters those affects the setup and hold time of the same?
If I want to change it, how to change it?
 

Thanks for the reply,
But this page only defines what is setup & hold time.
It doesn't defines on what parameter both of this timing depends..?
According to my logic: I think setup time depends on the driver strength & hold time depends on the delay of the capture flop...
 

The latency and rise /fall time of each gate affects these parameters.
IF you design looks like this then it is typical for most CMOS.
1622569400_1438364125.jpg
 
Thanks for the reply.
So will there be any way to modify the setup & hold time once after the circuit is made?
 

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