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How would one verify an SDRAM controler in simulation

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matrixofdynamism

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I am aware that when designing SDRAM controllers, it is important to not just be aware of how the SDRAM works but also be careful about the tight timing requirements. Now with emphasis on this second aspect, how would one go about verifying an SDRAM controller design written in a HDL? Do manufacturers of SDRAMs provide some sort of behavioural model for this purpose?

SDRAMs are common with FPGAs and I know that I can find a ready-made controller for this task. I am asking this question out of curiosity.
 

Go to Micron's web site and select the SDRAM from their products and then select a device on that page and you'll find the simulation models.

If SDRAM isn't what you want, then look in the DDR2/3/4 product pages for models of those devices.
 
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