Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Is the following legal in VHDL?

Status
Not open for further replies.
S

shaiko

Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,644
Helped
303
Reputation
608
Reaction score
297
Trophy points
1,363
Activity points
18,302
Hello,

Is the following legal in VHDL?

Code: 
process ( clock ) is
begin
  if rising_edge (clock) then
     y ( to_integer ( pointer ) + 8 downto to_integer ( pointer ) ) <= x ; -- pointer isn't a constant 
  end if ;
end process ;
 

Are you still using this forum as a VHDL compiler?
yes it's legal VHDL. But might not work as expected as a synthesisor (ive seen odd results from quartus - but that was a few years ago).
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Are you still using this forum as a VHDL compiler?
Click to expand...
Not today :)
This time my question comes after the fact.

I have a synthesis process with a similar block of code stuck at >45 minutes (Synplify, not Quartus).
Logic wise, I'm asking the tool to implement a bunch of muxes - nothing special...

I remember however that there's a VHDL rule that states that the boundaries on the right side of "downtown" must be static or something like that...
Can you remind me please about it?
 

Its legal VHDL - otherwise it wouldnt have got past the elaboration phase (and it wouldnt be 45 minutes in).
Slow synths often come from large memories that didnt infer ram primitives.

Why not try running the synth with a case statement instead to see if this actually is the problem?
 

Why not try running the synth with a case statement instead
Click to expand...
That's my next move.
I just wanted to make it elegant instead of a huge ugly case (pointer is 8 bits wide!).

otherwise it wouldnt have got past the elaboration phase
Click to expand...
I know. I'm not impling that this is the case here...
I simply remember that VHDL has restricitions on using non constant values for boundaries under some circumstances. I forgot the exact restriction - do you remember it?
 

shaiko said:
I remember however that there's a VHDL rule that states that the boundaries on the right side of "downtown" must be static or something like that...
Can you remind me please about it?
Click to expand...

That is a Verilog rule for the following:

Code: 
assign y[n +:9] = x;
The width of the slice must be static

The equivalent to your example would be:
Code: 
assign y[n+8 : n] = x;
which is also okay.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
shaiko said:
I simply remember that VHDL has restricitions on using non constant values for boundaries under some circumstances. I forgot the exact restriction - do you remember it?
Click to expand...

A case statement must have locally static slice boundaries.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
It looks like a synthesis tool problem/limitation and not at language issue.

Have you tried to slice the assignment to avoid the "downto" ?

Something like this (not tested):

Code: 
process (clock) is
begin
  if rising_edge (clock) then
    for i in x'range loop
     y(to_integer(pointer) + i) <= x(i) ;
    end for;
  end if ;
end process ;
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top