What is meant by clocked external delay?

While synthesizing a design in RTL Compiler, I reported the timing using report timing -lint command.
I got a warning message as follows:
********************************************
Inputs without clocked external delays

The following primary inputs have no clocked external delays. As a result the
timing paths leading from the ports have no timing constraints derived from
clock waveforms. The'external_delay' command is used to create new external
delays.

/designs/minsoc_top/ports_in/jtag_tdi
/designs/minsoc_top/ports_in/jtag_tms
/designs/minsoc_top/ports_in/reset
********************************************

I had specified input and external delays using set_input_delay and set_output_delay commands. Why I am getting this warning message?? What is "clocked external delays"?

You will not have specified the input_delays for the reset port and the jtag ports. That should be the reason. Reset should be fine I suppose. Not sure about the jtag ports..

Thanks for the response Sharath.
It was my mistake. I had not given the clock name in the set_input_delay command.
When I give like
set_input_delay 100 -clock jtag_clk jtag_tdi
it works fine.

Difference between external_delay and set_input_delay commands?

What is the difference between the following two commands in Cadence RTL Compiler?

1. external_delay -input 500 -clock jtag_clk jtag_tdi
2. set_input_delay 500 -clock jtag_clk jtag_tdi