Post simulation error ; rcx extraction error

I have drawn the layout
checked DRC and LVS

while extracting the layout the reisitors are not getting extracted

pls help


this is the error showing in cadence viruoso


Delete psf data in /root/simulation/PMOSTEST/spectre/schematic/psf.
generate netlist...
Begin Incremental Netlisting Jul 6 05:33:48 2015
WARNING (OSSHNL-160): The primitive, 'sample/pcapacitor/spectre', was not used in the last netlisting session in this
current run directory. Therefore, re-netlisting all cell views where this
primitive is instantiated.

WARNING (OSSHNL-160): The primitive, 'analogLib/presistor/spectre', was not used in the last netlisting session in this
current run directory. Therefore, re-netlisting all cell views where this
primitive is instantiated.

ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch av_extracted veriloga', for the
instance 'R2' in cell 'PMOSLAYOUT'. Either add one of these views to the library 'gpdk180',
cell 'polyres' or modify the view list to contain an existing view.

End netlisting Jul 6 05:33:48 2015
ERROR (OSSHNL-514): Netlisting failed due to errors reported before. Netlist may be corrupt or may not be produced at all. Fix reported errors and netlist again.
...unsuccessful.

I guess you have to include the sample and analogLib libraries to the Model Library Setup.