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in UPF, how to constraint the related_pg_pin for a input pin of a hard macro

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oprabho

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Hi,
I have a power-domain PD in which a dual voltage memory macro is instantiated. The primary supply of PD is VDD1. The macro has dual supply of VDD1 and VDD2. The VDD2 is used by internal of the memory macro and all the input/ouput of the macro are on VDD1 supply, except for input IN1 which is on ythe VDD2 supply. So, I need to model this scenario in UPF as the input to IN1 whose sink is in VDD2, will require the level-shifter from VDD1 to VDD2.
My question is how do I model this scenario in UPF.

Thanks
Prabho
 

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