dpaul
Advanced Member level 5
Hi,
I have a design in which there is compiler directive named "BFM".
It is defined in one of the include files as `define BFM and by default is enabled.
The purpose of this `define is to make a connection to a certain module in my top-level test-bench and is meant to be used only during simulation for a certain test. Consequently some of my 'to be synthesized' design also has this BFM directive and there is a corresponding `else part too.
I synthesize my design for FPGA using Synopsys Pro.
Following is my synthesis script.
Naturally I do not want the part inside `ifdef BFM to be synthesized.
I tried the hdl_define -clear "BFM" Synplify command in my synth script but it doesn't help.
If I completely exclude the statement hdl_define -clear "BFM" from my script then also there is no difference (I did a tkdiff of the synth log files).
Is anybody familiar with other Synopsys Pro commands such that I can explicitely specify not to synthesize anything that comes within BFM directive in my synthesis script?
I have a design in which there is compiler directive named "BFM".
It is defined in one of the include files as `define BFM and by default is enabled.
The purpose of this `define is to make a connection to a certain module in my top-level test-bench and is meant to be used only during simulation for a certain test. Consequently some of my 'to be synthesized' design also has this BFM directive and there is a corresponding `else part too.
I synthesize my design for FPGA using Synopsys Pro.
Following is my synthesis script.
Code:
set HW_TOP $::env(HW_TOP)
# Open a new Project
project -new
# ------------------------------------------------------------------------
# Set the target technology, part number, package, and speed grade options
# ------------------------------------------------------------------------
set_option -technology SPARTAN6
set_option -part XC6SLX150
set_option -package CSG484
set_option -speed_grade -2
#set_option -disable_io_insertion 1
set_option -synthesis_onoff_pragma 1
set_option -log_file te0630_top_axi.log
set_option -include_path "$HW_TOP/src/fpga/"
set_option -include_path "$HW_TOP/src/includes/"
set_option -write_verilog 1
set_option -write_vhdl 0
#set_option -write_vif 1
hdl_define -clear "BFM"
# -------------------------
# Load all the necessary design files
# -------------------------
#Core files
# Top-level design file
add_file -constraint te0630_top.sdc
impl -add te0630_top_axi -type fpga
# Set top level module
set_option -top_module te0630_top
#set result format/file last
project -result_file "te0630_top_axi.edf"
# Save the existing Project to a file.
project -save "te0630_top_axi.prj"
# Synthesize the existing Project
project -runNaturally I do not want the part inside `ifdef BFM to be synthesized.
I tried the hdl_define -clear "BFM" Synplify command in my synth script but it doesn't help.
If I completely exclude the statement hdl_define -clear "BFM" from my script then also there is no difference (I did a tkdiff of the synth log files).
Is anybody familiar with other Synopsys Pro commands such that I can explicitely specify not to synthesize anything that comes within BFM directive in my synthesis script?
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