shaiko
Advanced Member level 5
Hello,
As far as I understand, configuration in VHDL is used to bind an entity with a desired architecture.
When will it be necessary to do so?
Why not have both on the same file in the first place?
As far as I understand, configuration in VHDL is used to bind an entity with a desired architecture.
When will it be necessary to do so?
Why not have both on the same file in the first place?