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Usage of VHDL configuration

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shaiko

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Hello,

As far as I understand, configuration in VHDL is used to bind an entity with a desired architecture.

When will it be necessary to do so?
Why not have both on the same file in the first place?
 

When will it be necessary to do so?

When you need the bind a specific entity to a specific archutecture. I have never used one (and its one of those areas people dont really understand and hardly ever use)

Why not have both on the same file in the first place?

When you have a simulation model and a synthesis model (maybe for performance reasons).
 
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    shaiko

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VHDL also allows entity instantiation which performs a similar function:

Code:
u1 : entity libraryName.entityName(architectureName) -- eg, work.alu(rtl)
  generic map( ...)
  port map( ... );

The architecture is optional when only one exists. The architecture name can't be a generic (unless this was changed). This style is becoming more popular as it allows libraries to be used effectively, and removes then need for component declarations.

Multiple architectures are rare outside of simulation.
 
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    shaiko

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This style is becoming more popular as it allows libraries to be used effectively, and removes then need for component declarations.

Can you please give a more detailed example of a design that uses these features?
 

Can you please give a more detailed example of a design that uses these features?

This is just direct instantiation that has been around since VHDL '93. It allows you to avoid the use of components, potentially speeding up debugging, as you dont have to wait for the map stage to see that a component doesnt match an entity.
 
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    shaiko

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