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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 signal clk_en_div_8 : std_logic; signal div_cnt : unsigned(2 downto 0) := "000"; process(clk) begin if rising_edge(clk) then div_cnt <= div_cnt + 1; if div_cnt = 0 then clk_en_div_8 <= '1'; else clk_en_div_8 <= '0'; end if; end if; end process;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 process(clk) begin if rising_edge(clk) then if clk_en_div_8 = '1' then --code here runs at 1/8 clock speed end if; end if; end process;