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Input current of OpAmp

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Safa_R

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Hi all;

I recently used TL072 op amp in my desgn. This op amp is J-FET input and according to its datasheet, its input current should be in range of pA. However, I measure 1 to 8 mA current in both + and - pins of the IC. I really confused that how it can possible !!?
The design is a voltage-control current sink/source and attached to the post.

Can anyone help me?
 

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The manufacturer doesn't quote a maximum current at the TL082 input pins but as they are direct connections to the gates of JFETs, I'm pretty sure you are measuring wrongly or your op-amp is fried.

Brian.
 

However, I measure 1 to 8 mA current in both + and - pins of the IC.

..."+ and - pins of the IC" - are you measuring the currents at the SIGNAL inputs or at the supply pins?
 

I mean inverting and non-inverting signal inputs, not supply pins.

- - - Updated - - -

The manufacturer doesn't quote a maximum current at the TL082 input pins but as they are direct connections to the gates of JFETs, I'm pretty sure you are measuring wrongly or your op-amp is fried.

Brian.

Thank u Brain.
But I'm sure about my measurements. I measured voltage across R2 and RL and they are about 8.3 and 0.2 volt respectively. Op-amp may damage. But It is new! This is the first time I use it. How it can be fried?
 

Those are voltages, your post title and first message say input currents. To measure the current you must break the connection at pins 2 & 3, one at a time, and connect the test meter across the break.

Brian.
 

Those are voltages, your post title and first message say input currents. To measure the current you must break the connection at pins 2 & 3, one at a time, and connect the test meter across the break.
Brian.

The voltages across R2 and RL are NOT caused by the opamps input currents. They simply form a voltage divider connected to GROUND!.
 

Sorry. There is a mistake here. In the schematic which uploaded here RL=10k ohm while I tested my circuit with RL=1k ohm. So, when voltage across RL is 0.2 volt it means 0.2mA passes through it. Similarly 8.3mA passes through R2!
It is a simple KCL. There is no way for current except pin 2 of the op-amp.
 

.............
It is a simple KCL. There is no way for current except pin 2 of the op-amp.
Of course there is. What about transistors Q6 and Q16?
As you have been told, you need to break the connection to the input to the op amp and connect the meter in series with the input.
But it's unlikely your meter will be able to measure such a low current.
 

Actually, there are two 10 ohm resistors in collector of Q16 and Q6 for check point. I used them only for measuring output current of these transistors without breaking connections. Reading their voltage says me that current of Q16 and Q6 is 0.2mA and approximately zero respectively.

I'm pretty sure you are measuring wrongly or your op-amp is fried.

I changed my op-amp but the problem remains. Do you have any suggestion that why my circuit may damaged op-amps, Brian?
 

Your schematic has the V5 polarity connected backwards.
No. Consider the negative voltage setting.

I understand that the problem is observed in a real circuit. So we should better ask for real voltage measurements at all OP pins.
 

You circuit must be unstable (oscillating)from feedback phase shift as 8.2v/11k is not the same as 0.3V/1k in output shared current.

... Edit.. What does scope say? And what is the total load ...caution wire capacitance and inductance in layout.
1k+1k?

This is design does not bias FETs properly and seems poor in general.

It may need AC load of 100 Ohms in series with 0.1uF to ground to suppress oscillations.

much better ways to make a +/-30V 100uA or 1mA VC-CS with fewer devices.
 

No. Consider the negative voltage setting.
Of course I saw that.
Why does the stupid SIM software wrongly show the positive terminal of the battery at -15V?? If somebody is wiring it then they must guess which is correct??
 

Of course I saw that.
Why does the stupid SIM software wrongly show the positive terminal of the battery at -15V?? If somebody is wiring it then they must guess which is correct??
There's nothing wrong with this, and it's not the software but the user who decided to draw the schematic this way. It may be more intuitive to set the voltage to +15 and connect the negative voltage source terminal to the negative OP supply pin. Both ways result in supplying the OP correctly.
 

FET bias from OpAmp is not adequate voltage to turn on.

Excess gain and 3 stage phase shift may oscillate.

This should be done with CB level shifter , not common drain/emitter inverter.
 

Thank u SunnySkyguy.

I'm aware that this circuit may have stability problem. As a result, I also checked voltages with oscilloscope to ensure stability.
Can you explain me more about biasing of FETs. I design this using a famous circuit for precision current sink/source.

Are you mean Voltage Controlled-Common Source from VC-CS?
 

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