shedo
Junior Member level 1
Hi all,
I'm trying to generate a "Name Mapping File" for primetime px, starting from a sldb description of "DW_ram_rw_s_dff.v". For normal design with verilog source I don't have any problems but if I use a sldb description (dw_foundation.sldb), design compiler generate an empty "Name Mapping File".
For the simulation I used the verilog code provided by synopsys.
This is my piece of code to generate the Name Mapping File:
I attach my full script and the log.
Syn script: View attachment syn.tcl.txt
Px script: View attachment tim_rtlvcd.tcl.txt
Syn log: View attachment log_syn.txt
Do you have any idea how to solve the problem?
The presence of "Name Mapping File" affects a lot on the estimate of consumption?
Thanks for your help!
I'm trying to generate a "Name Mapping File" for primetime px, starting from a sldb description of "DW_ram_rw_s_dff.v". For normal design with verilog source I don't have any problems but if I use a sldb description (dw_foundation.sldb), design compiler generate an empty "Name Mapping File".
For the simulation I used the verilog code provided by synopsys.
This is my piece of code to generate the Name Mapping File:
Code:
saif_map -start
...
sh vcd2saif -input ../sim/rtlvcd.dump -output ./rtlvcd.saif
saif_map -review -create_map -source_instance test/u0 -input ./rtlvcd.saif
saif_map -report
saif_map -write_map ./aes_cipher_ptpxmap.tcl -type ptpxI attach my full script and the log.
Syn script: View attachment syn.tcl.txt
Px script: View attachment tim_rtlvcd.tcl.txt
Syn log: View attachment log_syn.txt
Do you have any idea how to solve the problem?
The presence of "Name Mapping File" affects a lot on the estimate of consumption?
Thanks for your help!