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Analog Interview Question: determine drain current for cascode

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I was asked that two nmos in a cascode topology, the bottom nmos source connected to ground. The two nmos gates were biasing by Vb1 and Vb2, where Vb2>Vb1>Vth.

Question: As we sweep the drain node of the top nmos Vd from 0V to some very large voltage, how the drain current change with Vd?
 

SunnySkyguy said:
Since both are saturated, it would look like a zener at 2*Vth
Click to expand...

Sorry, I didn't get what you were saying. I thought the two nmos will operate first at linear region, and then as the drain voltage became large enough, they will operate at saturation region. So the Id vs Vd plot is the same as the Id vs Vds plot for single nmos at certain Vgs.

Please let me know if I am wrong.
 

In cascode connection, the lower device provides voltage gain, the upper device isolation between drain and the lower gate.
If the upper gate is fed from a fixed dc voltage source (as it usually is) this pretty much fixes the current through the whole device, and sweeping the drain voltage will have little or no effect on drain current once drain voltage is above some minimal threshold.

That is the whole idea behind the cascode connection.
You can get extremely high voltage gain without the capacitive "Miller"coupling back between the drain (output) and the lower gate (input).

The whole device will act pretty much as a constant current sink independent of drain voltage over a very wide range.
 
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