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DFF chain using a for loop

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shaiko

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Hello,

I want to design a chain of 'n' number DFFs to delay an input signal.
Instead of using a shift register - I want to use the loop statement.
This is what I wrote:

Code:
signal dff_chain : std_logic_vector ( n - 1 downto 0 ) ;

process ( clock ) is 
begin
    if reset = '1' then
        dff_chain <= ( others => '0' ) ;
    elsif rising_edge ( clock ) then	
        dff_chain ( 0 ) <= input ;
        for index in dff_chain ' range
        loop
           dff_chain ( index + 1 ) <= dff_chain ( index  ) ;
        end loop ;
    end if ;
end process ;	

delayed_input <= dff_chain ( dff_chain ' high ) ;

Will it work?
 

I'm not sure the index + 1 will be within 'range. Won't range be (n-1 downto 0)? This would mean that index + 1 will be n.

Though what you are doing is a shift register.
 
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    shaiko

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Code:
signal dff_chain : std_logic_vector ( n - 1 downto 0 ) ;

process ( clock ) is 
begin
    if reset = '1' then
        dff_chain <= ( others => '0' ) ;
    elsif rising_edge ( clock ) then	
        dff_chain ( 0 ) <= input ;
        for index in dff_chain ' range
        loop
           dff_chain ( index + 1 ) <= dff_chain ( index  ) ;
        end loop ;
    end if ;
end process ;	

delayed_input <= dff_chain ( dff_chain ' high ) ;

Will it work?

Nope - because your loop variables goes out of range of the array (a great example of how using a simulator would be a lot quicker than posting the question on the forum and asking)

Instead of using a shift register - I want to use the loop statement.

You are building a shift register.
 
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    shaiko

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a great example of how using a simulator would be a lot quicker than posting the question on the forum and asking
Still looking for a good simulator that can run on a Galaxy S5...

Nope - because your loop variables goes out of range of the array
Missed that, thanks.

Suppose I rewrite it as:

Code:
process ( clock ) is 
begin
    if reset = '1' then
        dff_chain <= ( others => '0' ) ;
    elsif rising_edge ( clock ) then	
        dff_chain ( 0 ) <= input ;
        for index in 0 to dff_chain ' length - 2
        loop
           dff_chain ( index + 1 ) <= dff_chain ( index ) ;
        end loop ;
    end if ;
end process ;

I assume it would work fine...
Now just for the sake of learning - please help me rewrite the same code using variables instead of signals.
Will it simply be:

Code:
process ( clock , reset ) is 
variable dff_chain : std_logic_vector ( n - 1 dowtno 0 ) ;
begin
    if reset = '1' then
        dff_chain := ( others => '0' ) ;
    elsif rising_edge ( clock ) then	
        dff_chain ( 0 ) := input ;
        for index in 0 to dff_chain ' length - 2
        loop
           dff_chain ( index + 1 ) := dff_chain ( index ) ;
        end loop ;
    end if ;
end process ;
 

Now just for the sake of learning - please help me rewrite the same code using variables instead of signals.
Will it simply be:

Code:
process ( clock , reset ) is 
variable dff_chain : std_logic_vector ( n - 1 dowtno 0 ) ;
begin
    if reset = '1' then
        dff_chain := ( others => '0' ) ;
    elsif rising_edge ( clock ) then	
        dff_chain ( 0 ) := input ;
        for index in 0 to dff_chain ' length - 2
        loop
           dff_chain ( index + 1 ) := dff_chain ( index ) ;
        end loop ;
    end if ;
end process ;

No, it doesn't work. There will be no delay since the input value will be assigned to all bits in dff_chain every clock cycle.
I should work if you do the assignments in the reverse order:

Code:
for index in dff_chain ' length - 2 downto 0 loop
    dff_chain(index + 1) := dff_chain (index);
end loop;
dff_chain(0) := input;

You also must assign dff_chain(n-1) to something, otherwise everything will be optimized away.
That assignment order will also work if dff_chain is a signal, since the order of signal assignments doesn't matter.
 
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    shaiko

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Why?
What's the difference?

Because otherwise all the assignments are made in the same clock (remember variables are assigned immediately). So if they assigned sequentially then the 0th value is passed all the way up the chain in a single clock - hence no shift register.
 
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    shaiko

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To avoid these confusions with assignment order, you'll use signals rather than variables, as in your first post.
 

To avoid these confusions with assignment order, you'll use signals rather than variables, as in your first post.
That's what I usually do.
It's an educational question.

- - - Updated - - -

Another question:
When is it absolutely necessary to assign a default value to the variable?
 

That's what I usually do.
It's an educational question.

- - - Updated - - -

Another question:
When is it absolutely necessary to assign a default value to the variable?

When you need it to start with the given default value.
 
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    shaiko

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Another question:
When is it absolutely necessary to assign a default value to the variable?

Never, but if the variable somewhere in the process is read before it is assigned registers will be created so the previous value can be accessed.
 
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    shaiko

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If you don't initialize the value and read it - wouldn't it create a latch under some circumstances ?
 

If you don't initialize the value and read it - wouldn't it create a latch under some circumstances ?

Probably, if you do it in a combinatorial process and the tools accept the code.
That should be similar to connecting inputs to outputs for a combinatorial process.
 
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    shaiko

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@shaiko:
you may also want to avoid using variables for inferring registers, or give them a clear name. This usage of variables adds an order-dependence that normally doesn't exist. If you want locally declared signals, you can put the process inside of a block or if-true-generate.

Most (all?) FPGA tools will assign all uninitialized ff's to 0. Simulation doesn't do this, so you should initialize variables (or not initialize them) for the simulation behavior.
 

you may also want to avoid using variables for inferring registers, or give them a clear name
What do you mean by: "clear name" ?

This usage of variables adds an order-dependence that normally doesn't exist.
Please give a code example of what you mean.
 

Most (all?) FPGA tools will assign all uninitialized ff's to 0. Simulation doesn't do this, so you should initialize variables (or not initialize them) for the simulation behavior.

This is really only true for Xilinx, Altera used to (<=Cyclone III, <=Stratix IV) stipulated that registers were not guaranteed to power up to a 0 or a 1 regardless of how you specified the register is reset. Altera may have changed this in their more recent parts, but I haven't read their datasheets for quite a few years.

It should be noted the paragraph about this only appears in one place and is something like 3 sentences long with nothing to denote it's importance, and it's buried within a much larger section with lots of other information. Last time I looked for it (to prove to another engineer why I was adding some stupid counter to a power up reset in the part), it took me half a day searching through the documents to find it.

Xilinx has a GSR net that is invisible to the user that guarantees the startup state of all registers in the device when done goes active.

- - - Updated - - -

What do you mean by: "clear name" ?


Please give a code example of what you mean.

This is one order of statements
a := b;
c := a;
c and a are equal to b
swapping the order of statements
c := a;
a := b;
c = a and a = b
will simulate differently.

whereas
a <= b;
c <= a;
and
c <= a;
a <= b;
will simulate exactly the same
c = a and a = b
 
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    shaiko

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This is really only true for Xilinx, Altera used to (<=Cyclone III, <=Stratix IV) stipulated that registers were not guaranteed to power up to a 0 or a 1 regardless of how you specified the register is reset. Altera may have changed this in their more recent parts, but I haven't read their datasheets for quite a few years.
Dont' agree. Altera implements power on reset state according to initialiting statements and default 0 POR state, as long as there are no contradicting logic specifications (e.g. different asynchronous reset). In this case you get a clear warning.
 

FvM, Disagree all you want, but I'm not going to spend time looking for that paragraph in their own documentation again. I thought it was ridiculous they didn't have a specific power on state for every flip-flop in the device, but it was in their documentation, and the other engineer I showed it to was just as surprised as I was.
 

What do you mean by: "clear name" ?

A clear name might include "reg", "_r", "_d", "_q", or whatever your team uses for a similar purpose. Variables that infer registers are typically used as locally declared registers. However, the construct doesn't do this unless special steps are taken with the read/write ordering. The naming scheme can at least tell another developer that you did intend to create only a register.
 
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    shaiko

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FvM, Disagree all you want, but I'm not going to spend time looking for that paragraph in their own documentation again. I thought it was ridiculous they didn't have a specific power on state for every flip-flop in the device, but it was in their documentation, and the other engineer I showed it to was just as surprised as I was.

Look at the bottom of page 13-44 in this document:

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts_qii51007.pdf

"Registers in the device core always power up to a low (0) logic level on all Altera devices. If your design specifies a power-up level other than 0, synthesis tools can implement logic that causes registers to behave as if they were powering up to a high (1) logic level."
 

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