Chethan Chethu
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Hi, i have written code for vga interface with Virtex-2 board.. Now i need to use the same code for virtex-5 board with slight changes in .ucf file.. But the signal lines are a bot different in both.. especially "vga_out_pixel_clock" line.. can any one help me..??
UCF of Virtex-2:
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "aj15" ;
NET "reset" LOC = "ac11" ;
NET "vga_B<0>" LOC = "d15" ;
NET "vga_B<1>" LOC = "e15" ;
NET "vga_B<2>" LOC = "h15" ;
NET "vga_B<3>" LOC = "j15" ;
NET "vga_B<4>" LOC = "c13" ;
NET "vga_B<5>" LOC = "d13" ;
NET "vga_B<6>" LOC = "d14" ;
NET "vga_B<7>" LOC = "e14" ;
NET "vga_comp_synch" LOC = "g12" ;
NET "vga_G<0>" LOC = "g10" ;
NET "vga_G<1>" LOC = "e10" ;
NET "vga_G<2>" LOC = "d10" ;
NET "vga_G<3>" LOC = "d8" ;
NET "vga_G<4>" LOC = "c8" ;
NET "vga_G<5>" LOC = "h11" ;
NET "vga_G<6>" LOC = "g11" ;
NET "vga_G<7>" LOC = "e11" ;
NET "vga_h_sync" LOC = "b8" ;
NET "vga_out_blank" LOC = "a8" ;
NET "vga_out_pixel_clock" LOC = "h12" ;
NET "vga_R<0>" LOC = "g8" ;
NET "vga_R<1>" LOC = "h9" ;
NET "vga_R<2>" LOC = "g9" ;
NET "vga_R<3>" LOC = "f9" ;
NET "vga_R<4>" LOC = "f10" ;
NET "vga_R<5>" LOC = "d7" ;
NET "vga_R<6>" LOC = "c7" ;
NET "vga_R<7>" LOC = "h10" ;
NET "vga_v_sync" LOC = "d11" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
UCF of Virtex-2:
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "aj15" ;
NET "reset" LOC = "ac11" ;
NET "vga_B<0>" LOC = "d15" ;
NET "vga_B<1>" LOC = "e15" ;
NET "vga_B<2>" LOC = "h15" ;
NET "vga_B<3>" LOC = "j15" ;
NET "vga_B<4>" LOC = "c13" ;
NET "vga_B<5>" LOC = "d13" ;
NET "vga_B<6>" LOC = "d14" ;
NET "vga_B<7>" LOC = "e14" ;
NET "vga_comp_synch" LOC = "g12" ;
NET "vga_G<0>" LOC = "g10" ;
NET "vga_G<1>" LOC = "e10" ;
NET "vga_G<2>" LOC = "d10" ;
NET "vga_G<3>" LOC = "d8" ;
NET "vga_G<4>" LOC = "c8" ;
NET "vga_G<5>" LOC = "h11" ;
NET "vga_G<6>" LOC = "g11" ;
NET "vga_G<7>" LOC = "e11" ;
NET "vga_h_sync" LOC = "b8" ;
NET "vga_out_blank" LOC = "a8" ;
NET "vga_out_pixel_clock" LOC = "h12" ;
NET "vga_R<0>" LOC = "g8" ;
NET "vga_R<1>" LOC = "h9" ;
NET "vga_R<2>" LOC = "g9" ;
NET "vga_R<3>" LOC = "f9" ;
NET "vga_R<4>" LOC = "f10" ;
NET "vga_R<5>" LOC = "d7" ;
NET "vga_R<6>" LOC = "c7" ;
NET "vga_R<7>" LOC = "h10" ;
NET "vga_v_sync" LOC = "d11" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE