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Full CHip netlist in COnformal

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nohj_yar

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Hi all,

I'm doing a FEV on RTL vs full-chip netlist, but the problem is during modelling the revised(full chip) design, it is stuck at 96%..

What are the practical reasons for this?

THanks for your help..
 

did you runs in flat or hierarchical mode?
I believed you also handle carefully the gated clock (if inserted), the multiplier identification.
 

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