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Altera Avalon ST parameters

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shaiko

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Hello,

In the Altera Avalon bus spec:

https://www.altera.com/content/dam/...US/pdfs/literature/manual/mnl_avalon_spec.pdf

Page 39:
"data" width is 1 up to 4096

Page 40:
"symbolsPerBeat" is 1 up to 32

Page 41:
"dataBitsPerSymbol" 1 up to 512

If the maximum number of "symbolsPerBeat" is set to 32 and the maximum number of "dataBitsPerSymbol" is set to 512 - then the maximum width of data shall be:
32 * 512 = 16,384

However, "data" is limited to 4096 bits (not 16,384 as it should have been)...

Am I missing something?
 

They are all allowable rules
Obviously cant have them all maxed at once or you break the data width rule

Why would you want such a big thing anyway?
 
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    shaiko

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I'm trying to build a generic Avalon wrapper.
So I want to make sure that this isn't a document error. I've seen another version of this spec with different rules.

- - - Updated - - -

Another example:

Page 41:
maxChannel - The maximum number of channels that a data
interface can support. 255 is the highest number.

Page 39:
channel - The channel number for data being transferred
on the current cycle. If an interface supports the channel signal, it must
also define the maxChannel parameter.

If 255 is the maximum channel number - why would you need a 128 bit vector to represent this number? Why not 8 bits???
 

Who knows - and to be honest who really cares
Avalon is an old spec that is being phased out - it was only ever supported by altera anyway. The only things that use it are altera IPs. Everyone else (even altera) now use AXI.
 

TrickyDicky said:
Who knows - and to be honest who really cares
Avalon is an old spec that is being phased out - it was only ever supported by altera anyway. The only things that use it are altera IPs. Everyone else (even altera) now use AXI.
Click to expand...

My sentiments exactly.

Also even if it is defined as a 128-bit vector instead of 8-bit, the synthesis/par tools will remove the unused logic anyways, so who cares. I've gotten used to IP from Altera and Xilinx producing 10,000 warnings in synthesis and PaR.
 

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