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What is difference between pass by ref and pass by val in systemverilog?

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what is difference between pass by ref and pass by val in systemverilog?

I just want to know what is difference between pass by ref and pass by val in systemverilog?

I can't find any example.also expecially, what is this?

Does anyone know what is this and explain?

interface xxx ...
event yyy;
event ggg;
event ggg1;
event ggg2;

modport io_bus ( ref yyy, ref ggg, ref ggg1, ref ggg2, .... );

endinterface


What is the purpose "ref yyy" in the modport ?
 

A ref will behave like a pointer in C - ie. there is only 1 variable, but 2 ways to get at it and modify it. So this way you need to remember that with refs, the value of yyy just points to an already existing value.

for pass by val, it makes a local copy of that variable when the function/task/whatever is called. It means it will not affect the outside world.
 

Argument passing is verbosely discussed in the LRM IEEE 1800-2012. I think it would be a good idea to read the specification before asking others to retell it.
 

TrickyDicky said:
A ref will behave like a pointer in C - ie. there is only 1 variable, but 2 ways to get at it and modify it. So this way you need to remember that with refs, the value of yyy just points to an already existing value.

for pass by val, it makes a local copy of that variable when the function/task/whatever is called. It means it will not affect the outside world.
Click to expand...

Thanks I don't know how does event works as ref in modport? From you said what it is like pointer.
I mean that yyy is just trigger so how does it works like pointer?
 

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