[Moved] What is the optimum number of decoupling caps

With decoupling caps it is obviously ideal if you have a set for every IC on a board.

But depending on how many IC's you have and space available for the circuit board, at some point on set of decoupling caps for every single IC may be impractical.

So what rule of thumb do you pros use to balance what is ideal with what is practical?

This comes down to the design of the PDN, and can open a can of worms when dealing with fast logic.
The approach tends to differ depending on just how fast your edge rates are (and are required to be), power for a 12Gb/s serdes is a very different animal from power for a few TL072 and 4000 series parts in a guitar pedal.

All that said, unless you are making a million units, 0402 caps are so cheap as to be nearly free, and fitting them is usually **MUCH** cheaper then a board respin.

Regards, Dan.

Hi,

it all depends on the circuit. How many switching signals? What active parts? What switching current? What signal waveform, especially dU/dt and dI/dt?

But on a sensitive circuit i try to decouple each single supply pin with a capacitor next to the pin.
Read datasheets, application notes and designnotes of every (critical) device. Usually the manufacturers give useful hints.

I´m sure some circuits work with only one capacitor. Back in the 80´s is saw a lot of pcbs like that. But the speed was low, and the number of switched lines also.

Nowadays we have lower signal levels, much more integrated and complex circuits on a much smaller area. And high frequency.

So i can´t give you a rule of thumb on this.

Klaus

KlausST said:

Hi,

it all depends on the circuit. How many switching signals? What active parts? What switching current? What signal waveform, especially dU/dt and dI/dt?

But on a sensitive circuit i try to decouple each single supply pin with a capacitor next to the pin.
Read datasheets, application notes and designnotes of every (critical) device. Usually the manufacturers give useful hints.

I´m sure some circuits work with only one capacitor. Back in the 80´s is saw a lot of pcbs like that. But the speed was low, and the number of switched lines also.

Nowadays we have lower signal levels, much more integrated and complex circuits on a much smaller area. And high frequency.

So i can´t give you a rule of thumb on this.

Klaus

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What if I be more specific.

Just hobby circuits that are not low power nor particularly sensitive to noise or anything like that.

12V power, 0.1mA - 2A currents, frequencies up to 100kHz or so.

Can you give me a very broad rule of thumb based on that?

As Dan pointed out, the cost of erring in the side of caution is typically less costly then having to redesign and remanufacture a PCB or the hassle of implementing the required kluges later to correct an issue.

The cost of the required decoupling caps, is often minimal compared to the hair pulling and frustration which can often ensue without them.

Also, as Klaus alluded to, many of today's microcontrollers and FPGAs/CPLDs have several V_DD, V_SS, AV_DD and AV_SS lines which all should be decoupled by their own individual decoupling caps as close to the device as possible.


BigDog

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boylesg said:

Just hobby circuits ...

Click to expand...

Posting schematics of your typical "hobby circuits" would probably be more helpful.

Well, as an example, if I had two CMOS logic chips soldered in side by side on a matrix board, would one 100nF decoupling cap between them be sufficient?

Is a 100nF cap sufficient to decouple CMOS logic chips, opamps and comparators - that seemed to be the consensus from some googling I did.

That depends on the CMOS, 4000 series will probably be fine, HC series might be ok, and some of the modern fast stuff will probably be problematic.

For opamps you need to consider the output current loop and the fact that it returns to the supply pins, if running a split supply with load referenced to ground then 2 caps are usually indicated.

Comparators it depends on the speed of the part.

Get a grab bag of 100nF caps and use them, it is just less hassle then trying to debug problems caused by being too frugal.

Regards, Dan.

Dan Mills said:

That depends on the CMOS, 4000 series will probably be fine, HC series might be ok, and some of the modern fast stuff will probably be problematic.

For opamps you need to consider the output current loop and the fact that it returns to the supply pins, if running a split supply with load referenced to ground then 2 caps are usually indicated.

Comparators it depends on the speed of the part.

Get a grab bag of 100nF caps and use them, it is just less hassle then trying to debug problems caused by being too frugal.

Regards, Dan.

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Single supply - split supplies are not really necessary for sort of circuits I am making at present.

Some rules of thumb:

It's easier to not fit a component than to kludge one in where there is no pads for it.

You always need 1 more than you thought you needed, or perhaps you added 1 too many.

Hi there,
Power supply lines are like a river - looks quiet but it's very lively and noisy, very noisy and full of waves close up.

Good practice is (at least) one decoupling cap per IC (and more if they have a lot of IO pins), as close to the pins as possible, so they aren't disturbed by adjacent devices and likewise don't disturb either.
Another orientating very rough rule of thumb is that generally 100pF (or less if you do the calculations) for high speed switching devices, 100nF for 40xx type ICs, 1uF for insurance against disturbing other devices on the PSN, and maybe even 10uF for noisy things like 555s.
Apparently, it's good practice (or it isn't, depending on what you read) to parallel capacitors of the same value, can't remember why right now but it makes a lot of sense. Also, apparently there's no harm in scaling caps that are paralleled so long as they have a ratio of 10:1, e.g. 1uF:100nF:1000pF.
Looking at photos of circa 1960's circuits there are few caps in sight, looking at current circuit boards you'll see they are filled to the brim with minute SMD caps under and around the microprocessors, if that helps.
I personally wouldn't have any ICs sharing 1 decoupling capacitor as that is no longer decoupling, that's what the filter caps at the circuit input are for. And OTT personal opinion - I try to avoid aluminium electrolytics like the plague unless it can't be helped due to capacitance needs/PCB space/budget, and ceramic are a touch wobbly too where temperature and stability are concerned.

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Hi again, took a moment to remember how to attach pdfs/docs, etc. I have a low frequency brain.
Here's a folder of useful stuff about decoupling and bypassing, if anyone who's interested can bear to read through it - well worth the time though if you skip the parts that are irrelevant to your needs.

Also, this web has some interesting stuff about capacitors:
**broken link removed**

Specifically:
**broken link removed**


View attachment Capacitor Bypassing and Decoupling info.rar

Never leave home without a handful of passive components in your pocket, especially capacitors.

Design Rules were always 1 cap per IC. (0.01 to 0.1uF) but have the rules changed with faster CMOS and higher drive currents today? Well, they were relaxed for 74HCxxx and CD4xxx types since they were low current and high Zout (200~300 OHms) But newer CMOS for the last decade is 10x lower impedance ( 25 or 50) and much faster.

The spikes in the supply are due to distributed Vcc track inductance and switched load capacitance where we know Ic=C*dv/dt product., limited by the ESR of driver. The voltage spike depends on the ratio of load/supply impedance as an impedance voltage divider for transients. Since the logic output switches a small capacitive load with very low ESR and the overall transmission line impedance ratios of the signal / power supply rails end up controlling the step size of the voltage spike. This is a combination of distributed inductance, resistance and capacitance from transmission line theory. Therefore the best decoupling cap is the one with the lowest ESR & ESL and not the value of the capacitor. Thus smaller case size SMD are preferred over TH caps. The self resonant frequency must be higher than the highest transition frequency of the logic device possible or related to the rise time by approx BW=1/(Tr+Tf), which is often 500 MHz

If you can't justify using less decoupling caps, I suggest you continue to use 1 per synchronous IC and then share 1 per 5 asynchronous IC's in small/medium scale integrate devices.

Let's see if Murata agrees with me.

https://www.murata.com/~/media/webrenewal/support/library/catalog/products/emc/emifil/c39e.ashx.

For HCMOS the Zo was 200~300 Ohms, LV cmos is ~ 50 Ohms and ALV cmos is ~ 25 Ohms drive impedance. Check for yourself, compute VOL rise for rated current to determine ESR ( due to RdsOn) there are over 50 CMOS families but driver impedance has dropped to 25 Ohms for best compromise between impedance mismatch and drive current. THen compute what is Vp for V=L di/dt where "di" could be Vcc/ESR and dt= rise time and L can be 1 nH/".

IMHO the best decoupling cap will have the lowest impedance at the band associated with device max switching speed. This usually means close the Series Resonant frequency or SRF of around 500MHz which often is in the 470pF range for 402's

Your choice of cap vendor specs will vary widely.