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SDC "create_clock" command

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shaiko

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Hello,

An example of "create_clock" SDC command:
Code: 
create_clock -period 10 -waveform {0 5} -name [COLOR="#FF0000"]clk[/COLOR][[COLOR="#0000CD"]get_ports [/COLOR]clk]

1. Does "clk" (marked in red) reffers to the HDL name of the signal ?
2. What is the purpose of "get_ports" (marked in blue) command ?
 

1.clk is not the HDL name. It is a name which the DC_Shell understands and it relates this name to that clock element.
2.get_ports is used to make certain that the tool understands clk as a port.
So the above command treats the port 'clk' as a clock and gives it the name 'clk'.
 
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1.clk is not the HDL name. It is a name which the DC_Shell understands and it relates this name to that clock element.
Click to expand...
So how do I actually tie the constrain to the actual HDL name in the design ?

get_ports is used to make certain that the tool understands clk as a port.
Click to expand...
create_clock -period 10 -waveform {0 5} -name clk[get_ports clk]
So the red "clk" is a name of what?
What does the blue "clk" stand for?
Can the red and the blue be different words?
 

the clk in red is just the name of the clock inside the SDC file (basically a local variable)
the get_ports searches for a net called clk in the top level of the design (because no heirarchy was written).
 
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the get_ports searches for a net called clk in the top level of the design (because no heirarchy was written).
Click to expand...
So the blue one is the actual HDL name?
If my top entity looks like this:

Code: 
entity some_entity is
port 
(
   my_clock : in std_logic
) ;
end entity ;

The SDC command can be:
create_clock -period 10 -waveform {0 5} -name any_name_i_like [get_ports my_clock]
?
 

shaiko said:
So the blue one is the actual HDL name?
If my top entity looks like this:

Code: 
entity some_entity is
port 
(
   my_clock : in std_logic
) ;
end entity ;

The SDC command can be:
create_clock -period 10 -waveform {0 5} -name any_name_i_like [get_ports my_clock]
?
Click to expand...

Yes
Ive seen it done
and it can get very confusing because "any_name_I_like" is what you see in all the timing reports.

Also note - there is a comand called "create_generated_clocks" which allows the STA to create clocks through PLLs etc. They are usually given their entire path name in the timing reports
 
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TrickyDicky,
the get_ports searches for a net called clk in the top level of the design (because no heirarchy was written).
Click to expand...
How can I make it look inside a lower heirarchy?
Also, Is this command applies only to entity ports? Or it can also be used for signals?
 

I highly suggest you read this document:
**broken link removed**

get_ports applies only to the top level of the design (I was in error before)
you could also use:
get_pins : returns the pins of any design unit (memories, ffs, luts)
get_nets : returns all the net names
 

Nobody uses this command for pins within a hierarchy. You will have to use create_generated_clock to define a clock within a hierarchy..
 

Reading the Altera SDC API...
https://www.altera.com/content/dam/a...mnl_sdctmq.pdf
In page 19:

As far as I understand - this is used to declare a PLL generated clock...

create_clock -period 10 [get_ports clk]
Click to expand...
This line declares a clock at the top level.

Now lets take a look at the following line:
create_generated_clock -divide_by 2 -source [get_ports clk] -name clkdiv \ [get_registers clkdiv]
Click to expand...
Is clkdiv is the new generated clock ?
What is the purpose of the '\' sign ?
What does [get_registers clkdiv] do ?
 

\ is a line continuation symbol in Tcl. SDC is based on Tcl so a lot of the language rules are the same.

You could easily write the following and it would work identically as the [get_<something> <some_identifier>] generates a list
create_generated_clock -divide_by 2 -source {clk} -name clkdiv {clkdiv}
Click to expand...

That's why you can do stuff like this for a bus and it will generate a list of all the bus pins.
set_input_delay -clock [get_ports clk] 10 [get_ports {in_bus[*]}]
Click to expand...
 
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Re: SDC &quot;create_clock&quot; command

it stands for registers.

- - - Updated - - -

from the doc:
Returns a collection of registers in the design.

get registers is not standard SDC - it is part of altera's stc_ext library.
 
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This is from the document - page 19:
# Create a clock and a divide-by-2 generated clock
create_clock -period 10 [get_ports clk]
create_generated_clock -divide_by 2 -source [get_ports clk] -name clkdiv [get_registers clkdiv]
Click to expand...
Isn't it an example of a PLL derived clock? What registers are there to refer to?
 

it's referencing the flip-flop instance clkdiv which is a badly designed ;-) divide by two using a toggle FF.

a generated clock from a PLL would be more like:

[get_pins {<some_auto_generated_heirarchy>/PLL_inst/CLKOUT0}]

or something similar, that references an actual pin of a primitive.
 
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Altera has the SDC command:
derive_pll_clocks

makes life easy!
 
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Altera has the SDC command:
derive_pll_clocks
Click to expand...
Yes, I've seen this one - thanks.

Can the Time Quest GUI create the SDC commands automatically?
 

If you look at the timequest gui - it has a tcl promt at the bottom. Anything you do in the gui can be copied/pasted from the tcl command line (in the command history). Whenever you save from timequest, it saves to an SDC file.
 
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