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how can i implement this delay element in vhdl?

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fahim1

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hi
i want to write structural code for this serial multiplier and this D block is just defined as an delay element,how can i write synthesizable code for this element???
hgg.PNG
 

The D stands for delay. It is nothing but a flip flop (a DFF).
 

I assume you know how to wire VHDL code for an adder and multiplier. You also now know that a delay element is nothing but a flip-flop (Sarath666's reply above). So create a basic entity containing the adder, multiplier and the delay-element. Later instantiate this entity as many times as you want. Referring to your figure, you need to connect a delay-element between each instantiated basic entity so as to get your desired functionality.
 
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sharath666 said:
The D stands for delay. It is nothing but a flip flop (a DFF).
Click to expand...
in the way u said i should do this multiply in six clks but i want to write this code and put t in a code that execute in one clk/?
how would that possible?
i think its too messy
 

To do it in 1 clock, remove all the delay elements..
 

fahim1 said:
hi
i want to write structural code for this serial multiplier and this D block is just defined as an delay element,how can i write synthesizable code for this element???
View attachment 118535
Click to expand...

fahim1 said:
in the way u said i should do this multiply in six clks but i want to write this code and put t in a code that execute in one clk/?
how would that possible?
i think its too messy
Click to expand...

That highlighted red text should have told you that it wouldn't work in 1 clock cycle.

Have you studied digital design? You're issues seem to be more of a problem with that than with actually writing HDL (ignoring all the typos you post).
 
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ads-ee said:
That highlighted red text should have told you that it wouldn't work in 1 clock cycle.

Have you studied digital design? You're issues seem to be more of a problem with that than with actually writing HDL (ignoring all the typos you post).
Click to expand...

thnx for ur help.
do u know why carry have a feedback with a delay to the same adder block???
 

I'd assume it's an unusual way to draw an accumulate.
 

for adding carry because i think otherwise the carry will be wasted???
 

Oops I wasn't think of a serial multiplier in my previous response, so the loop is to accumulate and the other line is probably a carry to the next stage. Didn't the "thesis paper" have any explanation of the block diagram?
 

ads-ee said:
Oops I wasn't think of a serial multiplier in my previous response, so the loop is to accumulate and the other line is probably a carry to the next stage. Didn't the "thesis paper" have any explanation of the block diagram?
Click to expand...
i didnt found anything.i copied the part of explanation of this adder.
333.PNG

- - - Updated - - -

i think the loop is carry, but i dont know what is the first line below the a0 except the loop?
 

Based on the text the loop is feeding back the carry.

I don't do any serial multiplication in FPGAs as I normally use the DSP hard IP if I need to do any multiplication, so I'm not familiar with the details of serial multipliers.
 

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