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Using Design Ware (synopsys) Example

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njr@1

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Dear All,

How to confirm if the re timing has worked in example (DW_mult_pipe
Stallable Pipelined Multiplier) given in design ware library?
There are two description as in before pipeline re timing and one after pipeline re timing, but while using balance register in synposys DC it does not allow re timing saying " No movable flip-flops in design. Nothing to re time".

Please let me know how to confirm the use of pipeline in this case ?

Thank you
 

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