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Why do we need verilog behavioural models ???

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raghavkmr

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Why do we need verilog behavioural models ??? and then why we need to do its equivalence checking with Spice Netlist
 

Because this way you can describe the working of a circuit in a simplest manner if compared to a structural model, releasing you of the task to predict all conditions and outputs covered by the designed circuit.
 

Behavioral models can do things that the limited set of
"compact models" (transistors & diodes and SPICE
internal primtives) cannot - those are fixed and only do
what was coded.

A blok where you only really care about the inputs,
outputs and their overt relation can solve much faster
behaviorally than in node-and-element detail.

But checking that those two are equivalent (enough)
is on you.
 

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