fravelalon
Newbie level 4
Hi, I designed a step-down converting circuit. I was able to get the simulation working but then I added a shunt resistor and the TSC101c currenst sensing amplifier and I get a convergence simulation issue. I tried the TSC101c model in an other circuit and it worked fine. Thank you for the help
View attachment 28Vto5V@2,2A-2015-05-23T14-46.zip
Schematic:
View attachment 28Vto5V@2,2A-2015-05-23T14-46.zip
Schematic:
Code:
Simulation results:
**** 05/23/15 16:30:36 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
** Profile: "SCHEMATIC1-bias" [ C:\Users\Marco\Documents\Cubesat\28vto5v@2,2a-pspicefiles\schematic1\bias.sim ]
**** CIRCUIT DESCRIPTION
******************************************************************************
** Creating circuit file "bias.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
*Libraries:
* Profile Libraries :
.INC "C:\Users\Marco\Documents\Cubesat\28vto5v@2,2a-pspicefiles\schematic1\bias\bias_profile.inc"
* Local Libraries :
* From [PSPICE NETLIST] section of C:\Users\Marco\AppData\Roaming\SPB_Data\cdssetup\OrCAD_PSpice/16.6.0/PSpice.ini file:
**** INCLUDING bias_profile.inc ****
.LIB ".\opamp_sr.lib"
.LIB ".\mos_n.lib"
.LIB ".\dx.lib"
.LIB ".\diode_vlim.lib"
.LIB ".\diode_novd.lib"
.LIB ".\diode_ilim.lib"
.LIB ".\tsc101c.lib"
.LIB ".\ina214.lib"
.LIB ".\d1n5820rl.lib"
.LIB ".\dmbra340t3.lib"
.LIB ".\tps54331_trans.lib"
.LIB ".\d1n5822.lib"
**** RESUMING bias.cir ****
.lib "nom.lib"
*Analysis directives:
.TRAN 0 8ms 0 SKIPBP
.OPTIONS ADVCONV
.AUTOCONVERGE ITL1=1000 ITL2=1000 ITL4=1000 RELTOL=0.05 ABSTOL=1.0E-6 VNTOL=.001 PIVTOL=1.0E-10
.PROBE64 V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
**** INCLUDING SCHEMATIC1.net ****
* source 28VTO5V@2,2A
X_U2 N14455 N14736 N15259 0 N14459 N15281 N15187 N14618 TPS54331_TRANS
C_C1 N14455 N14459 0.1u IC=0 TC=0,0
L_L1 N14459 N14484 12uH
C_C3 0 N14484 47u IC=0 TC=0,0
R_R1 N14618 N14484 10k TC=0,0
R_R2 0 N14618 1.87k TC=0,0
C_C4 N14736 0 120p IC=0 TC=0,0
C_C5 N14736 N14775 5600p IC=0 TC=0,0
R_R3 N14775 0 12.4k TC=0,0
C_C6 0 N15187 10u IC=0 TC=0,0
C_C7 0 N15187 10u IC=0 TC=0,0
R_R4 N15259 N15187 348k TC=0,0
R_R5 0 N15259 76.8k TC=0,0
C_C8 0 N15281 0.015u IC=0 TC=0,0
V_V2 N15187 0
+PWL 0 0 100u 12 10m 12
D_D1 0 N14459 D1N5820RL
R_R6 N14484 N19438 0.08 TC=0,0
R_R7 0 N19438 10 TC=0,0
C_C9 0 N14484 100n IC=0 TC=0,0
X_U3 N14484 N19438 N22296 N14484 0 TSC101C
.PARAM w=11u vcc_low=4 ro1=1 ro_source=3 vcc_high=24 vccp_enhance=-100m
+ a0=97.93103448e3 r1={a0/(gm_mos*gb*ro2_1)} iee=10u rd=1k vicm_low=2.8
+ cbw_c=0.243p l=1u av_a=20 av_b=50 gm_mos=0.0002348021861505248 ro2_1={ro -
+ ro2_2 - ro1} ro2_2=1e-3 av_c=100 vccn_enhance=-700m rg1=5k v_dprot=0.6
+ alpha_switch_ro=1e4 vd_compensazione=-245.4u gb=10m ro_off=0.82 ccomp=11p
+ iib=5.5e-6 ro=17587.2 rg3_c={av_c*rg1} vicm_high=30 ro_sink=1m
**** RESUMING bias.cir ****
.END
**** 05/23/15 16:30:36 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
** Profile: "SCHEMATIC1-bias" [ C:\Users\Marco\Documents\Cubesat\28vto5v@2,2a-pspicefiles\schematic1\bias.sim ]
**** Diode MODEL PARAMETERS
******************************************************************************
D1N5820RL X_U3.DIODE_NOVd X_U3.DIODE_VLIM X_U3.DIODE_ILIM
IS 1.000000E-03 10.000000E-15 800.000000E-18 800.000000E-18
N 2.34208 1.000000E-03
BV 20
IBV 2.000000E-03
RS .027467
CJO 636.939000E-12
VJ 1.5
M .364419
EG .550905
XTI 3.02706
X_U3.DX MBR340
IS 10.000000E-15 823.900000E-09
ISR 838.600000E-09
IKF .5654
RS .01827
CJO 477.200000E-12
VJ .75
M .4787
XTI 0
X_U2.X_U40_U1.DD
IS 900.000000E-21
X_U2.X_U48_D9.DD
IS 900.000000E-21
X_U2.X_U41_U2.DD DIODE_VLIM DIODE_NOVd
IS 900.000000E-21 800.000000E-18 10.000000E-15
N .2
**** 05/23/15 16:30:36 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
** Profile: "SCHEMATIC1-bias" [ C:\Users\Marco\Documents\Cubesat\28vto5v@2,2a-pspicefiles\schematic1\bias.sim ]
**** MOSFET MODEL PARAMETERS
******************************************************************************
X_U3.MOS_N MOS_N
NMOS NMOS
LEVEL 1 1
L 100.000000E-06 100.000000E-06
W 100.000000E-06 100.000000E-06
VTO .65 .65
KP 500.000000E-06 500
GAMMA 0 0
PHI .6 .6
LAMBDA 0 0
IS 10.000000E-15 10.000000E-15
JS 0 0
PB .8 .8
PBSW .8 .8
CJ 0 0
CJSW 0 0
CGSO 0 0
CGDO 0 0
CGBO 0 0
TOX 0 0
XJ 0 0
UCRIT 10.000000E+03 10.000000E+03
DIOMOD 1 1
VFB 0 0
LETA 0 0
WETA 0 0
U0 0 0
TEMP 0 0
VDD 5 5
XPART 0 0
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U45_IN2) = 12.21uV \ 0V
V(X_U2.U45_IN3) = 12.21uV \ 0V
V(X_U2.CLK) = 12.21uV \ 0V
V(X_U2.U45_IN4) = 12.21uV \ 0V
V(X_U2.U45_IN5) = 12.21uV \ 0V
V(X_U2.U43_N02780) = 29.00MV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET196) = 245.40uV \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.U45_N05307) = 16.28uV \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.U42_N14330317) = 244.13uV \ 0V
V(X_U2.X_U42_U_DFF1.qint) = 244.14uV \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qqq) = 244.14uV \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.U42_QN) = 244.13uV \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0110) = 245.40uV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0187) = -245.40uV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET125) = 245.40uV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0201) = -245.40uV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.clkdel) = 244.13uV \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.E_U47_ABM1) = -5.005nA \ 0A
I(X_U3.E59) = -248.09pA \ 0A
I(X_U3.E_VOH) = -248.18pA \ 0A
I(X_U3.EVLIM_HIGH_VRG3) = 248.18pA \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U41_V2) = -1.596pA \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.V_U42_V11) = 127.49nA \ 0A
I(X_U3.VVLIM_HIGH_VRG3) = 248.18pA \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
I(X_U2.X_U42_H1.VH_U42_H1) = 127.49nA \ 0A
I(X_U2.X_U42_U_DFF1.v1) = -1.427nA \ 0A
I(X_U2.X_U42_F2.VF_U42_F2) = 127.49nA \ 0A
I(X_U3.XIAMP_SR.V_ENHANCE_VCCN) = 1.221pA \ 0A
I(X_U3.XIAMP_SR.V_ENHANCE_VCCP) = -1.221pA \ 0A
I(X_U2.X_U42_H1.H_U42_H1) = -12.75pA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U3.DVLIM_LOW_VRG3 X_U2.X_U41_U3.d1
X_U2.X_U42_U_DFF1.d_d10 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U45_ABM9
X_U2.E_U43_ABM4 X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+06 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
ITL4 = 125
ABSTOL = 1.26e-010
VNTOL = 4.47e-005
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 649.21KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET196) = 245.40uV \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.U42_N14330317) = 244.13uV \ 0V
V(X_U2.X_U42_U_DFF1.qint) = 244.14uV \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qqq) = 244.14uV \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.U42_QN) = 244.13uV \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0110) = 245.40uV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0187) = -245.40uV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET125) = 245.40uV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0201) = -245.40uV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.clkdel) = 244.13uV \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.E_U47_ABM1) = -5.005nA \ 0A
I(X_U3.E59) = -248.09pA \ 0A
I(X_U3.E_VOH) = -248.18pA \ 0A
I(X_U3.EVLIM_HIGH_VRG3) = 248.18pA \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.V_U42_V11) = 127.49nA \ 0A
I(X_U3.VVLIM_HIGH_VRG3) = 248.18pA \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
I(X_U2.X_U42_H1.VH_U42_H1) = 127.49nA \ 0A
I(X_U2.X_U42_U_DFF1.v1) = -1.427nA \ 0A
I(X_U2.X_U42_F2.VF_U42_F2) = 127.49nA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U3.DVLIM_LOW_VRG3 X_U2.X_U41_U3.d1
X_U2.X_U42_U_DFF1.d_d10 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 649.2E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
ITL4 = 1000
ABSTOL = 1.58e-008
VNTOL = 0.001
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.V_U42_V11) = 127.49nA \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
I(X_U2.X_U42_H1.VH_U42_H1) = 127.49nA \ 0A
I(X_U2.X_U42_F2.VF_U42_F2) = 127.49nA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
ABSTOL = 1e-006
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
RELTOL = 0.0086
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
RELTOL = 0.05
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming could not converge the circuit, restarting it now
These voltages failed to converge:
V(N14736) = 4.516mV \ 3.956mV
V(N14775) = 4.516mV \ 3.956mV
V(X_U2.U48_N19630) = 5.000V \ 0V
V(X_U2.CLK) = 0V \ 12.21uV
V(X_U2.U43_N02780) = 5.000V \ 29.00KV
V(X_U2.U42_N14379753) = 0V \ 5.000V
V(X_U3.VRG3) = -29.06mV \ -49.85pV
V(X_U2.X_U43_U3.YINT1) = 5.000V \ 0V
V(X_U2.X_U43_U3.YINT2) = 6.260uV \ 0V
V(X_U2.X_U42_U_DFF1.qint) = -244.14uV \ 244.14uV
V(X_U2.X_U42_U_DFF1.qqq) = -244.14uV \ 244.14uV
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.VEE_N) = -2.491V \ -2.650MV
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.NET0123) = 916.70uV \ 61.72pV
V(X_U3.XIAMP_SR.NET0134) = -599.08mV \ -600.00mV
V(X_U3.XIAMP_SR.NET0116) = 578.11mV \ 600.00mV
V(X_U3.XIAMP_SR.NET0192) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.NET0115) = 578.11mV \ 600.00mV
V(X_U3.XIAMP_SR.NET096) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.NET0190) = 916.70uV \ 61.72pV
V(X_U3.XIAMP_SR.NET0135) = -599.08mV \ -600.00mV
V(X_U3.XIAMP_SR.VB) = 7.750uV \ -70.38fV
V(X_U3.XIAMP_SR.VB_3) = 7.708uV \ -70.38fV
V(X_U3.XIAMP_SR.VB_2) = 7.716uV \ -70.38fV
V(X_U3.XIAMP_SR.VOUT_DIFF) = 7.785mV \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = 7.135A \ -5.800A
I(X_U2.E_U48_ABM11) = -5.005nA \ 0A
I(X_U3.E67) = -7.708uA \ -9.50e-21A
I(X_U3.E59) = -144.63mA \ -248.09pA
I(X_U3.E64) = 7.003KA \ 16.12fA
I(X_U3.E_VOL) = 148.46nA \ 95.13fA
I(X_U3.E65) = -7.003KA \ -16.12fA
I(X_U3.E_VOH) = -144.63mA \ -248.18pA
I(X_U3.EVLIM_HIGH_VRG3) = 144.63mA \ 248.18pA
I(X_U3.EVLIM_LOW_VRG3) = -148.46nA \ -95.13fA
I(X_U2.X_U43_U3.E_ABMGATE1) = -5.000A \ 0A
I(X_U3.XIAMP_SR.E_VREF) = -7.708uA \ -9.91e-21A
I(X_U2.V_U41_V3) = -11.60A \ -10.16A
I(X_U2.V_U43_V8) = -169.88uA \ -170.07uA
I(X_U2.V_U43_V6) = -7.135A \ 5.800A
I(X_U3.VVLIM_LOW_VRG3) = 148.46nA \ 95.13fA
I(X_U3.VVLIM_HIGH_VRG3) = 144.63mA \ 248.18pA
I(X_U2.X_U43_F1.VF_U43_F1) = 169.88uA \ -138.09uA
I(X_U2.X_U42_U_DFF1.v1) = -1.029nA \ -1.427nA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCP) = -9.167uA \ -618.56fA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCN) = -7.003KA \ 1.221pA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCP) = 7.003KA \ -1.221pA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCP) = -9.167uA \ -618.56fA
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U3.DVLIM_LOW_VRG3 X_U2.X_U41_U3.d1
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U43_ABM4
X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Restarting Simulation with the following settings
ITL4 = 125
ABSTOL = 1.26e-010
VNTOL = 4.47e-005
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 649.21KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET196) = 245.40uV \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.U42_N14330317) = 244.13uV \ 0V
V(X_U2.X_U42_U_DFF1.qint) = 244.14uV \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qqq) = 244.14uV \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.U42_QN) = 244.13uV \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0110) = 245.40uV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0187) = -245.40uV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET125) = 245.40uV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0201) = -245.40uV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.clkdel) = 244.13uV \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.E_U47_ABM1) = -5.005nA \ 0A
I(X_U3.E59) = -248.09pA \ 0A
I(X_U3.E_VOH) = -248.18pA \ 0A
I(X_U3.EVLIM_HIGH_VRG3) = 248.18pA \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.V_U42_V11) = 127.49nA \ 0A
I(X_U3.VVLIM_HIGH_VRG3) = 248.18pA \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
I(X_U2.X_U42_H1.VH_U42_H1) = 127.49nA \ 0A
I(X_U2.X_U42_U_DFF1.v1) = -1.427nA \ 0A
I(X_U2.X_U42_F2.VF_U42_F2) = 127.49nA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U3.DVLIM_LOW_VRG3 X_U2.X_U41_U3.d1
X_U2.X_U42_U_DFF1.d_d10 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 649.2E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
ITL4 = 1000
ABSTOL = 1.58e-008
VNTOL = 0.001
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.V_U42_V11) = 127.49nA \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
I(X_U2.X_U42_H1.VH_U42_H1) = 127.49nA \ 0A
I(X_U2.X_U42_F2.VF_U42_F2) = 127.49nA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
ABSTOL = 1e-006
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
RELTOL = 0.0086
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
RELTOL = 0.05
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming could not converge the circuit, restarting it now
These voltages failed to converge:
V(N14736) = 4.516mV \ 3.956mV
V(N14775) = 4.516mV \ 3.956mV
V(X_U2.U48_N19630) = 5.000V \ 0V
V(X_U2.U43_N02780) = 5.000V \ 29.00KV
V(X_U2.U42_N14379753) = 0V \ 5.000V
V(X_U3.VRG3) = -29.06mV \ -49.85pV
V(X_U2.X_U43_U3.YINT1) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qint) = -244.14uV \ 244.14uV
V(X_U2.X_U42_U_DFF1.qqq) = -244.14uV \ 244.14uV
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.VEE_N) = -2.491V \ -2.650MV
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.NET0123) = 916.70uV \ 61.72pV
V(X_U3.XIAMP_SR.NET0134) = -599.08mV \ -600.00mV
V(X_U3.XIAMP_SR.NET0116) = 578.11mV \ 600.00mV
V(X_U3.XIAMP_SR.NET0192) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.NET0115) = 578.11mV \ 600.00mV
V(X_U3.XIAMP_SR.NET096) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.NET0190) = 916.70uV \ 61.72pV
V(X_U3.XIAMP_SR.NET0135) = -599.08mV \ -600.00mV
V(X_U3.XIAMP_SR.VOUT_DIFF) = 7.785mV \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = 7.135A \ -5.800A
I(X_U2.E_U48_ABM11) = -5.005nA \ 0A
I(X_U3.E67) = -7.708uA \ -9.50e-21A
I(X_U3.E59) = -144.63mA \ -248.09pA
I(X_U3.E64) = 7.003KA \ 16.12fA
I(X_U3.E_VOL) = 148.46nA \ 95.13fA
I(X_U3.E65) = -7.003KA \ -16.12fA
I(X_U3.E_VOH) = -144.63mA \ -248.18pA
I(X_U3.EVLIM_HIGH_VRG3) = 144.63mA \ 248.18pA
I(X_U3.EVLIM_LOW_VRG3) = -148.46nA \ -95.13fA
I(X_U2.X_U43_U3.E_ABMGATE1) = -5.000A \ 0A
I(X_U3.XIAMP_SR.E_VREF) = -7.708uA \ -9.91e-21A
I(X_U2.V_U41_V3) = -11.60A \ -10.16A
I(X_U2.V_U43_V8) = -169.88uA \ -170.07uA
I(X_U2.V_U43_V6) = -7.135A \ 5.800A
I(X_U3.VVLIM_LOW_VRG3) = 148.46nA \ 95.13fA
I(X_U3.VVLIM_HIGH_VRG3) = 144.63mA \ 248.18pA
I(X_U2.X_U43_F1.VF_U43_F1) = 169.88uA \ -138.09uA
I(X_U2.X_U42_U_DFF1.v1) = -1.029nA \ -1.427nA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCP) = -9.167uA \ -618.56fA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCN) = -7.003KA \ 1.221pA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCP) = 7.003KA \ -1.221pA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCP) = -9.167uA \ -618.56fA
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U3.DVLIM_LOW_VRG3 X_U2.X_U41_U3.d1
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U43_ABM4
X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Restarting Simulation with the following settings
ITL4 = 1000
ABSTOL = 1.58e-008
VNTOL = 0.001
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.V_U42_V11) = 127.49nA \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
I(X_U2.X_U42_H1.VH_U42_H1) = 127.49nA \ 0A
I(X_U2.X_U42_F2.VF_U42_F2) = 127.49nA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
ABSTOL = 1e-006
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
RELTOL = 0.0086
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
RELTOL = 0.05
Convergence problem in transient analysis at Time = 6.104E-15
Time step = 6.104E-15, minimum allowable step size = 8.000E-15
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -10.16A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 3.517E-09 (N14459) 3.517E-09 (N14484)-140.8E-15 (N14618) 901.8E-15
(N14736) .0040 (N14775) .0040 (N15187) 5.859E-09 (N15259) .0629
(N15281) 6.510E-12 (N19438)-436.5E-09 (N22296)-70.38E-15 (X_U2.OC) 127.5E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 5.859E-09
(X_U2.CLK) 12.21E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-70.38E-15 (X_U3.VRG3)-49.85E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 5.859E-09 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 244.1E-06 (X_U3.NET185)-140.8E-15
(X_U3.NET191)-70.38E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-70.38E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-70.38E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-140.8E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-20.03E-18 (X_U3.VRG3_3)-8.051E-24
(X_U3.VRG3_4)-3.236E-30 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 12.21E-06
(X_U2.U45_IN3) 12.21E-06 (X_U2.U45_IN4) 12.21E-06
(X_U2.U45_IN5) 12.21E-06 (X_U2.VREF_GM) 5.866E-09
(X_U3.VRG3_SR)-70.38E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-70.38E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 127.5E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 5.859E-09 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 5.859E-09 (X_U2.U42_N01108) 3.517E-09
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 42.09E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 16.28E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-70.38E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-70.38E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 244.1E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-70.38E-15
(X_U3.XIAMP_SR.VB_3)-70.38E-15 (X_U3.XIAMP_SR.VREF)-70.38E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 244.1E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.72E-12 (X_U3.XIAMP_SR.NET0131)-140.8E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-140.8E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.72E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-140.8E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-70.38E-15 (X_U2.X_U42_U_DFF1.qint) 244.1E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 244.1E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming could not converge the circuit, restarting it now
These voltages failed to converge:
V(X_U2.U48_N19630) = 5.000V \ 0V
V(X_U2.U43_N02780) = 5.000V \ 29.00KV
V(X_U2.U42_N14379753) = 0V \ 5.000V
V(X_U3.VRG3) = -29.06mV \ -49.85pV
V(X_U2.X_U43_U3.YINT1) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.VEE_N) = -2.491V \ -2.650MV
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.NET0116) = 578.11mV \ 600.00mV
V(X_U3.XIAMP_SR.NET0192) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.NET0115) = 578.11mV \ 600.00mV
V(X_U3.XIAMP_SR.NET096) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.VOUT_DIFF) = 7.785mV \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = 7.141A \ -5.800A
I(X_U3.E67) = -7.708uA \ -9.50e-21A
I(X_U3.E59) = -144.63mA \ -248.09pA
I(X_U3.E64) = 7.003KA \ 16.12fA
I(X_U3.E65) = -7.003KA \ -16.12fA
I(X_U3.E_VOH) = -144.63mA \ -248.18pA
I(X_U3.EVLIM_HIGH_VRG3) = 144.63mA \ 248.18pA
I(X_U2.X_U43_U3.E_ABMGATE1) = -5.000A \ 0A
I(X_U3.XIAMP_SR.E_VREF) = -7.708uA \ -9.91e-21A
I(X_U2.V_U41_V3) = -11.60A \ -10.16A
I(X_U2.V_U43_V8) = -169.88uA \ -170.07uA
I(X_U2.V_U43_V6) = -7.141A \ 5.800A
I(X_U3.VVLIM_HIGH_VRG3) = 144.63mA \ 248.18pA
I(X_U2.X_U43_F1.VF_U43_F1) = 170.01uA \ -138.09uA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCP) = -9.167uA \ -618.56fA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCN) = -7.003KA \ 1.221pA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCP) = 7.003KA \ -1.221pA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCP) = -9.167uA \ -618.56fA
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U3.DVLIM_LOW_VRG3 X_U2.X_U41_U3.d1
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U43_ABM4
X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Restarting Simulation with the following settings
RELTOL = 0.0086
ABSTOL = 1e-006
Convergence problem in transient analysis at Time = 762.9E-18
Time step = 762.9E-18, minimum allowable step size = 930.4E-18
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -81.27A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 440.1E-12 (N14459) 440.1E-12 (N14484)-17.59E-15 (N14618) 112.7E-15
(N14736) .0040 (N14775) .0040 (N15187) 732.4E-12 (N15259) .0629
(N15281) 813.8E-15 (N19438)-436.5E-09 (N22296)-8.798E-15 (X_U2.OC) 15.99E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 732.4E-12
(X_U2.CLK) 1.526E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-8.798E-15 (X_U3.VRG3)-6.231E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 732.4E-12 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 30.52E-06 (X_U3.NET185)-17.59E-15
(X_U3.NET191)-8.798E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-8.798E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-8.798E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-17.59E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-313.0E-21 (X_U3.VRG3_3)-15.72E-27
(X_U3.VRG3_4) 0.0000 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 1.526E-06
(X_U2.U45_IN3) 1.526E-06 (X_U2.U45_IN4) 1.526E-06
(X_U2.U45_IN5) 1.526E-06 (X_U2.VREF_GM) 733.2E-12
(X_U3.VRG3_SR)-8.798E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-8.798E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 15.99E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 732.4E-12 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 732.4E-12 (X_U2.U42_N01108) 440.1E-12
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 5.262E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 2.035E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-8.798E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-8.798E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 30.52E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-8.798E-15
(X_U3.XIAMP_SR.VB_3)-8.798E-15 (X_U3.XIAMP_SR.VREF)-8.797E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 30.52E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.84E-12 (X_U3.XIAMP_SR.NET0131)-17.59E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-17.59E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.84E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-17.59E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-8.797E-15 (X_U2.X_U42_U_DFF1.qint) 30.52E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 30.52E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming Simulation with the following settings
RELTOL = 0.05
Convergence problem in transient analysis at Time = 762.9E-18
Time step = 762.9E-18, minimum allowable step size = 930.4E-18
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -81.27A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 440.1E-12 (N14459) 440.1E-12 (N14484)-17.59E-15 (N14618) 112.7E-15
(N14736) .0040 (N14775) .0040 (N15187) 732.4E-12 (N15259) .0629
(N15281) 813.8E-15 (N19438)-436.5E-09 (N22296)-8.798E-15 (X_U2.OC) 15.99E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 732.4E-12
(X_U2.CLK) 1.526E-06 (X_U2.ECO) 0.0000
(X_U3.VB_3)-8.798E-15 (X_U3.VRG3)-6.231E-12
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 732.4E-12 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 30.52E-06 (X_U3.NET185)-17.59E-15
(X_U3.NET191)-8.798E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-8.798E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-8.798E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-17.59E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-313.0E-21 (X_U3.VRG3_3)-15.72E-27
(X_U3.VRG3_4) 0.0000 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 1.526E-06
(X_U2.U45_IN3) 1.526E-06 (X_U2.U45_IN4) 1.526E-06
(X_U2.U45_IN5) 1.526E-06 (X_U2.VREF_GM) 733.2E-12
(X_U3.VRG3_SR)-8.798E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-8.798E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 15.99E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 732.4E-12 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 732.4E-12 (X_U2.U42_N01108) 440.1E-12
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 5.262E-09
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 2.035E-06
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-8.798E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-8.798E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 30.52E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-8.798E-15
(X_U3.XIAMP_SR.VB_3)-8.798E-15 (X_U3.XIAMP_SR.VREF)-8.797E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 30.52E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.84E-12 (X_U3.XIAMP_SR.NET0131)-17.59E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-17.59E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.84E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-17.59E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-8.797E-15 (X_U2.X_U42_U_DFF1.qint) 30.52E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 30.52E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming could not converge the circuit, restarting it now
These voltages failed to converge:
V(X_U2.U48_N19630) = 5.000V \ 0V
V(X_U2.U43_N02780) = 5.000V \ 29.00KV
V(X_U2.U42_N14379753) = 0V \ 5.000V
V(X_U3.VRG3) = -3.783mV \ -6.231pV
V(X_U2.X_U43_U3.YINT1) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.VEE_N) = -2.491V \ -2.650MV
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.NET0116) = 578.11mV \ 600.00mV
V(X_U3.XIAMP_SR.NET0192) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.NET0115) = 578.11mV \ 600.00mV
V(X_U3.XIAMP_SR.NET096) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.VOUT_DIFF) = 7.785mV \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = 7.141A \ -5.800A
I(X_U3.E67) = -7.708uA \ -9.50e-21A
I(X_U3.E59) = -150.62mA \ -248.09pA
I(X_U3.E64) = 7.003KA \ 16.12fA
I(X_U3.E65) = -7.003KA \ -16.12fA
I(X_U3.E_VOH) = -150.62mA \ -248.18pA
I(X_U3.EVLIM_HIGH_VRG3) = 150.62mA \ 248.18pA
I(X_U2.X_U43_U3.E_ABMGATE1) = -5.000A \ 0A
I(X_U3.XIAMP_SR.E_VREF) = -7.708uA \ -8.378e-21A
I(X_U2.V_U41_V3) = -92.74A \ -81.27A
I(X_U2.V_U43_V6) = -7.141A \ 5.800A
I(X_U3.VVLIM_HIGH_VRG3) = 150.62mA \ 248.18pA
I(X_U2.X_U43_F1.VF_U43_F1) = 170.01uA \ -138.09uA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCP) = -9.167uA \ -618.56fA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCN) = -7.003KA \ 1.221pA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCP) = 7.003KA \ -1.221pA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCP) = -9.167uA \ -618.56fA
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U3.DVLIM_LOW_VRG3 X_U2.X_U41_U3.d1
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U43_ABM4
X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Restarting Simulation with the following settings
RELTOL = 0.05
Convergence problem in transient analysis at Time = 95.37E-18
Time step = 95.37E-18, minimum allowable step size = 160.0E-18
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -650.18A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 55.02E-12 (N14459) 55.02E-12 (N14484)-2.199E-15 (N14618) 14.09E-15
(N14736) .0040 (N14775) .0040 (N15187) 91.55E-12 (N15259) .0629
(N15281) 101.7E-15 (N19438)-436.5E-09 (N22296)-1.101E-15 (X_U2.OC) 2.000E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 91.55E-12
(X_U2.CLK) 190.7E-09 (X_U2.ECO) 0.0000
(X_U3.VB_3)-1.101E-15 (X_U3.VRG3)-778.9E-15
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 91.55E-12 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 3.815E-06 (X_U3.NET185)-2.199E-15
(X_U3.NET191)-1.101E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-1.101E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-1.101E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-2.199E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-4.891E-21 (X_U3.VRG3_3)-30.71E-30
(X_U3.VRG3_4) 0.0000 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 190.7E-09
(X_U2.U45_IN3) 190.7E-09 (X_U2.U45_IN4) 190.7E-09
(X_U2.U45_IN5) 190.7E-09 (X_U2.VREF_GM) 91.65E-12
(X_U3.VRG3_SR)-1.101E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-1.101E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 2.000E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 91.55E-12 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 91.55E-12 (X_U2.U42_N01108) 55.02E-12
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 657.7E-12
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 254.3E-09
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-1.101E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-1.101E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 3.815E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-1.101E-15
(X_U3.XIAMP_SR.VB_3)-1.101E-15 (X_U3.XIAMP_SR.VREF)-1.100E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 3.815E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.85E-12 (X_U3.XIAMP_SR.NET0131)-2.199E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-2.199E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.85E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-2.199E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-1.100E-15 (X_U2.X_U42_U_DFF1.qint) 3.815E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 3.815E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming could not converge the circuit, restarting it now
These voltages failed to converge:
V(X_U2.U48_N19630) = 5.000V \ 0V
V(X_U2.U43_N02780) = 5.000V \ 29.00KV
V(X_U2.U42_N14379753) = 0V \ 5.000V
V(X_U2.X_U43_U3.YINT1) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.VEE_N) = -2.491V \ -2.650MV
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.NET0192) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.NET096) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.VOUT_DIFF) = 7.785mV \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = 7.141A \ -5.800A
I(X_U3.E67) = -7.708uA \ -9.50e-21A
I(X_U3.E59) = -151.40mA \ -248.09pA
I(X_U3.E64) = 7.003KA \ 16.12fA
I(X_U3.E65) = -7.003KA \ -16.12fA
I(X_U3.E_VOH) = -151.40mA \ -248.18pA
I(X_U3.EVLIM_HIGH_VRG3) = 151.40mA \ 248.18pA
I(X_U2.X_U43_U3.E_ABMGATE1) = -5.000A \ 0A
I(X_U3.XIAMP_SR.E_VREF) = -7.708uA \ -13.55e-21A
I(X_U2.V_U41_V3) = -741.84A \ -650.18A
I(X_U2.V_U43_V6) = -7.141A \ 5.800A
I(X_U3.VVLIM_HIGH_VRG3) = 151.40mA \ 248.18pA
I(X_U2.X_U43_F1.VF_U43_F1) = 170.01uA \ -138.09uA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCP) = -9.167uA \ -618.56fA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCN) = -7.003KA \ 1.221pA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCP) = 7.003KA \ -1.221pA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCP) = -9.167uA \ -618.56fA
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCN
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U43_ABM4 X_U3.XIAMP_SR.M_NMOS2
X_U3.XIAMP_SR.M_NMOS1
ERROR(ORPSIM-15138): Convergence problem in transient analysis at Time = 95.37E-18.
Time step = 95.37E-18, minimum allowable step size = 160.0E-18
These voltages failed to converge:
V(N14736) = 499.01mV \ 4.513mV
V(N14775) = 499.01mV \ 4.513mV
V(X_U2.U43_N02780) = 0V \ 5.000V
V(X_U3.VRG3) = -639.22mV \ -475.34uV
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -2.387MV \ 3.502MV
V(X_U3.XIAMP_SR.VEE_N) = -1.806V \ -2.491V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -2.387MV \ 3.502MV
V(X_U3.XIAMP_SR.NET0192) = -33.56mV \ -21.89mV
V(X_U3.XIAMP_SR.NET096) = -33.56mV \ -21.89mV
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = 4.942A \ 7.141A
I(X_U3.E59) = -203.60A \ -151.40mA
I(X_U3.E64) = -4.775KA \ 7.003KA
I(X_U3.E65) = 4.775KA \ -7.003KA
I(X_U3.E_VOH) = -203.60A \ -151.40mA
I(X_U3.EVLIM_HIGH_VRG3) = 203.60A \ 151.40mA
I(X_U2.V_U41_V3) = -82.02KA \ -741.84A
I(X_U2.V_U43_V8) = -341.30nA \ -169.88uA
I(X_U2.V_U43_V6) = -4.942A \ -7.141A
I(X_U3.VVLIM_HIGH_VRG3) = 203.60A \ 151.40mA
I(X_U2.X_U43_F1.VF_U43_F1) = 117.67uA \ 170.01uA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCN) = 4.775KA \ -7.003KA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCP) = -4.775KA \ 7.003KA
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U3.DVLIM_LOW_VRG3 X_U2.X_U41_U3.d1
X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2 X_U3.XIAMP_SR.M_NMOS2
X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 55.02E-12 (N14459) 55.02E-12 (N14484)-2.199E-15 (N14618)-346.4E-18
(N14736) .4990 (N14775) .4990 (N15187) 91.55E-12 (N15259) .0629
(N15281) 101.7E-15 (N19438)-436.5E-09 (N22296) 822.9E-12 (X_U2.OC) 1.999E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 0.0000
(X_U2.CLK) 0.0000 (X_U2.ECO) 0.0000
(X_U3.VB_3) 822.9E-12 (X_U3.VRG3) -.6392
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 0.0000 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 3.815E-06 (X_U3.NET185)-2.199E-15
(X_U3.NET191) 822.9E-12 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225) 822.9E-12 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249) 822.9E-12
(X_U3.NET257) 0.0000 (X_U3.NET261)-2.199E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-4.014E-09 (X_U3.VRG3_3)-25.20E-18
(X_U3.VRG3_4)-158.3E-27 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 190.7E-09
(X_U2.U45_IN3) 190.7E-09 (X_U2.U45_IN4) 190.7E-09
(X_U2.U45_IN5) 190.7E-09 (X_U2.VREF_GM)-31.81E-27
(X_U3.VRG3_SR) 822.9E-12 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK) 822.9E-12
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 1.999E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 91.55E-12 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 91.55E-12 (X_U2.U42_N01108) 55.02E-12
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 0.0000 (X_U2.U45_N00466) 657.7E-12
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 254.3E-09
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 5.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE) 822.9E-12 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB) 6.938E-06
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 3.815E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 0.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2) 6.937E-06
(X_U3.XIAMP_SR.VB_3) 6.930E-06 (X_U3.XIAMP_SR.VREF)-1.100E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 5.0000
(X_U2.X_U43_U3.YINT2) 97.81E-09 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N) -1.8062
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096) -.0336
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq)-3.815E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .5664 (X_U3.XIAMP_SR.NET0116) .5664
(X_U3.XIAMP_SR.NET0123) 916.7E-06 (X_U3.XIAMP_SR.NET0131)-2.199E-15
(X_U3.XIAMP_SR.NET0134) -.5991 (X_U3.XIAMP_SR.NET0135) -.5991
(X_U3.XIAMP_SR.NET0153)-2.199E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 916.7E-06 (X_U3.XIAMP_SR.NET0192) -.0336
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-2.199E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-1.100E-15 (X_U2.X_U42_U_DFF1.qint)-3.815E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) .0070 (X_U2.X_U42_U_DFF1.clkdel) 3.815E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS)-2.387E+06
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS)-2.387E+06
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
**** Interrupt ****
**** Param: RELTOL = 0.05
**** Param: ABSTOL = 1e-006
**** Param: VNTOL = 0.001
**** Param: GMIN = 1e-012
**** Param: TSTOP = 0.008
**** Param: TMAX = 0
**** Param: ITL1 = 150
**** Param: ITL2 = 20
**** Param: ITL4 = 1000
**** Param: AutoConverge = 1
**** Param: AutoConverge.ITL1 = 1000
**** Param: AutoConverge.ITL2 = 1000
**** Param: AutoConverge.ITL4 = 1000
**** Param: AutoConverge.RELTOL = 0.05
**** Param: AutoConverge.ABSTOL = 1e-006
**** Param: AutoConverge.VNTOL = 0.001
**** Param: AutoConverge.PIVTOL = 1e-010
**** Param: ADVCONV = 1
**** Param: Current_Simulation = 3
**** Param: METHOD = 0
**** Param: TRTOL = 7
**** Param: STEPGMIN = 0
**** Param: GMINSTEPS = 0
**** Param: ITL6 = 0
**** Param: NOSTEPDEP = 0
**** Param: PTRANSTEP = 0
**** Param: GMINSRC = 0
**** Param: PSEUDOTRAN = 0
**** Param: NOSTEPSRC = 0
**** Param: RELTOL = 0.05
**** Param: ABSTOL = 1e-006
**** Param: VNTOL = 0.001
**** Param: GMIN = 1e-012
**** Param: TSTOP = 0.008
**** Param: TMAX = 0
**** Param: ITL1 = 150
**** Param: ITL2 = 20
**** Param: ITL4 = 1000
**** Param: AutoConverge = 1
**** Param: AutoConverge.ITL1 = 1000
**** Param: AutoConverge.ITL2 = 1000
**** Param: AutoConverge.ITL4 = 1000
**** Param: AutoConverge.RELTOL = 0.05
**** Param: AutoConverge.ABSTOL = 1e-006
**** Param: AutoConverge.VNTOL = 0.001
**** Param: AutoConverge.PIVTOL = 1e-010
**** Param: ADVCONV = 1
**** Param: Current_Simulation = 3
**** Param: METHOD = 0
**** Param: TRTOL = 7
**** Param: STEPGMIN = 0
**** Param: GMINSTEPS = 0
**** Param: ITL6 = 0
**** Param: NOSTEPDEP = 0
**** Param: PTRANSTEP = 0
**** Param: GMINSRC = 0
**** Param: PSEUDOTRAN = 0
**** Param: NOSTEPSRC = 0
Convergence problem in transient analysis at Time = 95.37E-18
Time step = 95.37E-18, minimum allowable step size = 160.0E-18
These voltages failed to converge:
V(N14736) = 3.956mV \ 0V
V(N14775) = 3.956mV \ 0V
V(N15259) = 62.92mV \ 0V
V(X_U2.SD) = 5.000V \ 0V
V(X_U2.U41_N14122) = 500.00mV \ 0V
V(X_U2.U41_N02173) = 1.600V \ 0V
V(X_U2.U43_N02780) = 29.00KV \ 0V
V(X_U2.U47_N00154) = 5.000V \ 0V
V(X_U2.U42_N14378229) = 800.00mV \ 0V
V(X_U2.U42_N04959) = 5.000V \ 0V
V(X_U2.U42_N14379753) = 5.000V \ 0V
V(X_U3.NET206) = -640.25mV \ 0V
V(X_U3.NET200) = -640.00mV \ 0V
V(X_U3.RWAKE_VAL) = 81.00KV \ 0V
V(X_U3.val_vdep_source) = 129.50V \ 0V
V(X_U3.val_vdep_sink) = -299.50V \ 0V
V(X_U2.X_U45_U_INV1.YINT) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.my5) = 5.000V \ 0V
V(X_U2.X_U42_U_DFF1.qbr) = 5.000V \ 0V
V(X_U2.X_U42_U5.YINT3) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.VEE_N) = -2.650MV \ 0V
V(X_U3.XIAMP_SR.VCCN_ENHANCED) = -700.00mV \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0134) = -600.00mV \ 0V
V(X_U3.XIAMP_SR.VCCP_ENHANCED) = -100.00mV \ 0V
V(X_U3.XIAMP_SR.NET0116) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0115) = 600.00mV \ 0V
V(X_U3.XIAMP_SR.NET0135) = -600.00mV \ 0V
V(X_U2.X_U42_U_DFF1.x1.YINT3) = 5.000V \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = -5.800A \ 0A
I(X_U2.X_U45_U_INV1.E_ABMGATE) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.eqb) = -5.000A \ 0A
I(X_U2.X_U42_U5.E_ABMGATE2) = -5.000A \ 0A
I(X_U2.X_U42_U_DFF1.x1.E_ABMGATE2) = -5.000A \ 0A
I(V_V2) = -2.400A \ 0A
I(X_U2.V_U41_V3) = -650.18A \ 0A
I(X_U2.V_U43_V5) = -138.09uA \ 0A
I(X_U2.V_U43_V8) = -170.07uA \ 0A
I(X_U2.V_U43_V6) = 5.800A \ 0A
I(X_U2.X_U43_F1.VF_U43_F1) = -138.09uA \ 0A
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCP
X_U3.XIAMP_SR.DPROT_IN_M_VCCN X_U3.XIAMP_SR.DPROT_IN_P_VCCP
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U48_ABM11 X_U2.E_U43_ABM4
X_U2.E_U42_ABM10 X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2
X_U2.X_U42_U_DFF1.gq X_U3.XIAMP_SR.M_NMOS2 X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 55.02E-12 (N14459) 55.02E-12 (N14484)-2.199E-15 (N14618) 14.09E-15
(N14736) .0040 (N14775) .0040 (N15187) 91.55E-12 (N15259) .0629
(N15281) 101.7E-15 (N19438)-436.5E-09 (N22296)-1.101E-15 (X_U2.OC) 2.000E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 91.55E-12
(X_U2.CLK) 190.7E-09 (X_U2.ECO) 0.0000
(X_U3.VB_3)-1.101E-15 (X_U3.VRG3)-778.9E-15
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 91.55E-12 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 3.815E-06 (X_U3.NET185)-2.199E-15
(X_U3.NET191)-1.101E-15 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225)-1.101E-15 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249)-1.101E-15
(X_U3.NET257) 0.0000 (X_U3.NET261)-2.199E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-4.891E-21 (X_U3.VRG3_3)-30.71E-30
(X_U3.VRG3_4) 0.0000 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 190.7E-09
(X_U2.U45_IN3) 190.7E-09 (X_U2.U45_IN4) 190.7E-09
(X_U2.U45_IN5) 190.7E-09 (X_U2.VREF_GM) 91.65E-12
(X_U3.VRG3_SR)-1.101E-15 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK)-1.101E-15
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 2.000E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 91.55E-12 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 91.55E-12 (X_U2.U42_N01108) 55.02E-12
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 29.00E+03 (X_U2.U45_N00466) 657.7E-12
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 254.3E-09
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 0.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE)-1.101E-15 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB)-1.101E-15
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 3.815E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 5.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2)-1.101E-15
(X_U3.XIAMP_SR.VB_3)-1.101E-15 (X_U3.XIAMP_SR.VREF)-1.100E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 0.0000
(X_U2.X_U43_U3.YINT2) 0.0000 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N)-2.650E+06
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096)-9.278E-09
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq) 3.815E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .6000 (X_U3.XIAMP_SR.NET0116) .6000
(X_U3.XIAMP_SR.NET0123) 61.85E-12 (X_U3.XIAMP_SR.NET0131)-2.199E-15
(X_U3.XIAMP_SR.NET0134) -.6000 (X_U3.XIAMP_SR.NET0135) -.6000
(X_U3.XIAMP_SR.NET0153)-2.199E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 61.85E-12 (X_U3.XIAMP_SR.NET0192)-9.278E-09
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-2.199E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-1.100E-15 (X_U2.X_U42_U_DFF1.qint) 3.815E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) 0.0000 (X_U2.X_U42_U_DFF1.clkdel) 3.815E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS) -.1000
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS) -.1000
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
Resuming could not converge the circuit, restarting it now
These voltages failed to converge:
V(X_U2.U48_N19630) = 5.000V \ 0V
V(X_U2.U43_N02780) = 5.000V \ 29.00KV
V(X_U2.U42_N14379753) = 0V \ 5.000V
V(X_U2.X_U43_U3.YINT1) = 5.000V \ 0V
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.VEE_N) = -2.491V \ -2.650MV
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = 3.502MV \ -100.00mV
V(X_U3.XIAMP_SR.NET0192) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.NET096) = -21.89mV \ -9.278nV
V(X_U3.XIAMP_SR.VOUT_DIFF) = 7.785mV \ 0V
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = 7.141A \ -5.800A
I(X_U3.E67) = -7.708uA \ -9.50e-21A
I(X_U3.E59) = -151.40mA \ -248.09pA
I(X_U3.E64) = 7.003KA \ 16.12fA
I(X_U3.E65) = -7.003KA \ -16.12fA
I(X_U3.E_VOH) = -151.40mA \ -248.18pA
I(X_U3.EVLIM_HIGH_VRG3) = 151.40mA \ 248.18pA
I(X_U2.X_U43_U3.E_ABMGATE1) = -5.000A \ 0A
I(X_U3.XIAMP_SR.E_VREF) = -7.708uA \ -13.55e-21A
I(X_U2.V_U41_V3) = -741.84A \ -650.18A
I(X_U2.V_U43_V6) = -7.141A \ 5.800A
I(X_U3.VVLIM_HIGH_VRG3) = 151.40mA \ 248.18pA
I(X_U2.X_U43_F1.VF_U43_F1) = 170.01uA \ -138.09uA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCP) = -9.167uA \ -618.56fA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCN) = -7.003KA \ 1.221pA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCP) = 7.003KA \ -1.221pA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_P_VCCN) = -1.460uA \ -618.56fA
I(X_U3.XIAMP_SR.VPROT_IN_M_VCCP) = -9.167uA \ -618.56fA
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U2.X_U41_U3.d1 X_U3.XIAMP_SR.DPROT_IN_M_VCCN
X_U3.XIAMP_SR.DPROT_IN_P_VCCN X_U2.E_U43_ABM4 X_U3.XIAMP_SR.M_NMOS2
X_U3.XIAMP_SR.M_NMOS1
ERROR(ORPSIM-15138): Convergence problem in transient analysis at Time = 95.37E-18.
Time step = 95.37E-18, minimum allowable step size = 160.0E-18
These voltages failed to converge:
V(N14736) = 499.01mV \ 4.513mV
V(N14775) = 499.01mV \ 4.513mV
V(X_U2.U43_N02780) = 0V \ 5.000V
V(X_U3.VRG3) = -639.22mV \ -475.34uV
V(X_U3.XIAMP_SR.VO_DIFF_MINUS) = -2.387MV \ 3.502MV
V(X_U3.XIAMP_SR.VEE_N) = -1.806V \ -2.491V
V(X_U3.XIAMP_SR.VO_DIFF_PLUS) = -2.387MV \ 3.502MV
V(X_U3.XIAMP_SR.NET0192) = -33.56mV \ -21.89mV
V(X_U3.XIAMP_SR.NET096) = -33.56mV \ -21.89mV
These supply currents failed to converge:
I(X_U2.E_U44_ABM5) = 4.942A \ 7.141A
I(X_U3.E59) = -203.60A \ -151.40mA
I(X_U3.E64) = -4.775KA \ 7.003KA
I(X_U3.E65) = 4.775KA \ -7.003KA
I(X_U3.E_VOH) = -203.60A \ -151.40mA
I(X_U3.EVLIM_HIGH_VRG3) = 203.60A \ 151.40mA
I(X_U2.V_U41_V3) = -82.02KA \ -741.84A
I(X_U2.V_U43_V8) = -341.30nA \ -169.88uA
I(X_U2.V_U43_V6) = -4.942A \ -7.141A
I(X_U3.VVLIM_HIGH_VRG3) = 203.60A \ 151.40mA
I(X_U2.X_U43_F1.VF_U43_F1) = 117.67uA \ 170.01uA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCN) = 4.775KA \ -7.003KA
I(X_U3.XIAMP_SR.V_ENHANCE_VCCP) = -4.775KA \ 7.003KA
These devices failed to converge:
X_U3.DVLIM_HIGH_VRG3 X_U3.DVLIM_LOW_VRG3 X_U2.X_U41_U3.d1
X_U2.X_U43_U3.E_ABMGATE1 X_U2.G_U43_ABMI2 X_U3.XIAMP_SR.M_NMOS2
X_U3.XIAMP_SR.M_NMOS1
Last node voltages tried were:
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(N14455) 55.02E-12 (N14459) 55.02E-12 (N14484)-2.199E-15 (N14618)-346.4E-18
(N14736) .4990 (N14775) .4990 (N15187) 91.55E-12 (N15259) .0629
(N15281) 101.7E-15 (N19438)-436.5E-09 (N22296) 822.9E-12 (X_U2.OC) 1.999E-09
(X_U2.SD) 5.0000 (X_U2.2P5) 0.0000
(X_U2.CLK) 0.0000 (X_U2.ECO) 0.0000
(X_U3.VB_3) 822.9E-12 (X_U3.VRG3) -.6392
(X_U3.INBUF) 0.0000 (X_U2.ENREGS) 0.0000
(X_U2.N67875) 0.0000 (X_U2.N67893) 0.0000
(X_U2.N67911) 0.0000 (X_U2.N67943) 0.0000
(X_U2.N68245) 0.0000 (X_U2.N68385) 0.0000
(X_U2.U42_QN) 3.815E-06 (X_U3.NET185)-2.199E-15
(X_U3.NET191) 822.9E-12 (X_U3.NET196) 245.4E-06
(X_U3.NET200) -.6400 (X_U3.NET206) -.6402
(X_U3.NET225) 822.9E-12 (X_U3.NET245) 0.0000
(X_U3.NET246) 0.0000 (X_U3.NET249) 822.9E-12
(X_U3.NET257) 0.0000 (X_U3.NET261)-2.199E-15
(X_U3.NET277) 0.0000 (X_U3.NET282) 0.0000
(X_U3.VRG3_2)-4.014E-09 (X_U3.VRG3_3)-25.20E-18
(X_U3.VRG3_4)-158.3E-27 (X_U3.VRG3_5) 0.0000
(X_U3.VRG3_6) 0.0000 (X_U3.Vsense) 0.0000
(X_U2.U42_IN1) 0.0000 (X_U2.U45_IN2) 190.7E-09
(X_U2.U45_IN3) 190.7E-09 (X_U2.U45_IN4) 190.7E-09
(X_U2.U45_IN5) 190.7E-09 (X_U2.VREF_GM)-31.81E-27
(X_U3.VRG3_SR) 822.9E-12 (X_U3.VCCN_REF) 0.0000
(X_U3.V_Io_val) 0.0000 (X_U3.DELAY_GEN) 0.0000
(X_U3.RWAKE_VAL) 81.00E+03 (X_U3.VB_3_SINK) 822.9E-12
(X_U3.VDEP_SINK) 0.0000 (X_U2.U40_N14704) 0.0000
(X_U2.U41_N00409) 0.0000 (X_U2.U41_N02173) 1.6000
(X_U2.U41_N03360) 1.999E-09 (X_U2.U41_N14122) .5000
(X_U2.U42_N00618) 91.55E-12 (X_U2.U42_N00718) 0.0000
(X_U2.U42_N00836) 91.55E-12 (X_U2.U42_N01108) 55.02E-12
(X_U2.U42_N01674) 0.0000 (X_U2.U42_N04959) 5.0000
(X_U2.U43_N00392) 0.0000 (X_U2.U43_N01530) 0.0000
(X_U2.U43_N01763) 0.0000 (X_U2.U43_N02091) 0.0000
(X_U2.U43_N02780) 0.0000 (X_U2.U45_N00466) 657.7E-12
(X_U2.U45_N00859) 0.0000 (X_U2.U45_N05307) 254.3E-09
(X_U2.U47_N00154) 5.0000 (X_U2.U48_N19630) 5.0000
(X_U2.X_U46.YINT) 0.0000 (X_U3.IIB_VM_VAL) 0.0000
(X_U3.VB_3_SOURCE) 822.9E-12 (X_U3.VDEP_SOURCE) 0.0000
(X_U3.VSENSE_WAKE) 0.0000 (X_U3.XIAMP_SR.VB) 6.938E-06
(X_U2.U42_N14330309) 0.0000 (X_U2.U42_N14330317) 3.815E-06
(X_U2.U42_N14330321) 0.0000 (X_U2.U42_N14330333) 0.0000
(X_U2.U42_N14374249) 0.0000 (X_U2.U42_N14378229) .8000
(X_U2.U42_N14379753) 0.0000 (X_U2.X_U42_U4.YINT) 0.0000
(X_U2.X_U42_U6.YINT) 0.0000 (X_U2.X_U42_U8.YINT) 0.0000
(X_U3.val_vdep_sink) -299.5000 (X_U3.XIAMP_SR.VB_2) 6.937E-06
(X_U3.XIAMP_SR.VB_3) 6.930E-06 (X_U3.XIAMP_SR.VREF)-1.100E-15
(X_U2.X_U42_U5.YINT1) 0.0000 (X_U2.X_U42_U5.YINT2) 0.0000
(X_U2.X_U42_U5.YINT3) 5.0000 (X_U2.X_U43_U3.YINT1) 5.0000
(X_U2.X_U43_U3.YINT2) 97.81E-09 (X_U2.X_U43_U3.YINT3) 0.0000
(X_U3.waking-up_ctrl) 0.0000 (X_U3.XIAMP_SR.VEE_N) -1.8062
(X_U3.val_vdep_source) 129.5000 (X_U3.XIAMP_SR.NET096) -.0336
(X_U3.XIAMP_SR.NET125) 245.4E-06 (X_U2.X_U42_U_DFF1.my5) 5.0000
(X_U2.X_U42_U_DFF1.qbr) 5.0000 (X_U2.X_U42_U_DFF1.qqq)-3.815E-06
(X_U3.XIAMP_SR.NET0109) 0.0000 (X_U3.XIAMP_SR.NET0110) 245.4E-06
(X_U3.XIAMP_SR.NET0115) .5664 (X_U3.XIAMP_SR.NET0116) .5664
(X_U3.XIAMP_SR.NET0123) 916.7E-06 (X_U3.XIAMP_SR.NET0131)-2.199E-15
(X_U3.XIAMP_SR.NET0134) -.5991 (X_U3.XIAMP_SR.NET0135) -.5991
(X_U3.XIAMP_SR.NET0153)-2.199E-15 (X_U3.XIAMP_SR.NET0187)-245.4E-06
(X_U3.XIAMP_SR.NET0190) 916.7E-06 (X_U3.XIAMP_SR.NET0192) -.0336
(X_U3.XIAMP_SR.NET0201)-245.4E-06 (X_U3.XIAMP_SR.NET0210)-2.199E-15
(X_U3.XIAMP_SR.NET0224) 0.0000 (X_U3.XIAMP_SR.NET0238) 0.0000
(X_U3.XIAMP_SR.NET0250)-1.100E-15 (X_U2.X_U42_U_DFF1.qint)-3.815E-06
(X_U2.X_U45_U_INV1.YINT) 5.0000 (X_U2.X_U42_U_DFF1.qqqd1) 0.0000
(X_U3.XIAMP_SR.VOUT_DIFF) .0070 (X_U2.X_U42_U_DFF1.clkdel) 3.815E-06
(X_U2.X_U42_U_DFF1.clkint) 0.0000 (X_U2.X_U42_U_DFF1.x2.YINT) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x1.YINT3) 5.0000
(X_U2.X_U42_U_DFF1.x3.YINT1) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT2) 0.0000
(X_U2.X_U42_U_DFF1.x3.YINT3) 0.0000
(X_U3.XIAMP_SR.VO_DIFF_PLUS)-2.387E+06
(X_U3.val_vdep_sink_filtered) 0.0000
(X_U3.XIAMP_SR.VCCN_ENHANCED) -.7000
(X_U3.XIAMP_SR.VCCP_ENHANCED) -.1000
(X_U3.XIAMP_SR.VO_DIFF_MINUS)-2.387E+06
(X_U3.VAL_VDEP_SOURCE_FILTERED) 0.0000
**** Interrupt ****
Last edited by a moderator:
