Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

process statement in vhdl confusion

Status
Not open for further replies.
P

p11

Banned
Joined
Jan 25, 2014
Messages
177
Helped
0
Reputation
0
Reaction score
0
Trophy points
16
Activity points
0
please someone explain me in simple wprds that when to use process in vhdl , and which signals are to be added in the sensitivity list .i have read some tutorial but unable to understand clearly.
 

Think of a VHDL process as a block of code that obeys certain rules.
The statements, which describe the behavior in a process, are executed sequentially, in the order you specified them.
Once the last line is exited the values get updated. This repeats itself in an infinite loop.

The "sensitivity list" has no effect on the synthesized logic - it's used for simulation only.
Every time a signal in the sensitivity list is changes - the process is entered. Think of it as a "hint" to the simulator that tells it when to look evaluate the statements inside the process.
 

i.e for signal assignment , variable assignment , if-else , for, case ,while we need to do process . say suppose if we write

Code: 
begin
process (a,b )
begin
y <= a nand b ;
 end process;


is it correct ??
 

The process syntax is correct, but you don't need process for this simple combinational assignment. In so far, it's no good example.
 
For a sensitivity list, anything you expect to have an immediate effect on an output should be in the sensitivity list.
So, for an asynchronous circuit, you would put in any signal evaluated in an if statement, case statement or on the RHS of an assignment.
Or if you are using vhdl 2008, you can simply write

process(all)

and it will be evaluated when any signal inside the process changes.

If it is synchronous, you only ever update the outputs on the edge of the clock, so only the clock (and an async reset if you have one) needs to be in the sensitivity list.

This has some major use later on in behavioural modelling and testbenches, as there are some attributes (most usefully the 'transaction attribute) that are signals that can be used in the sensitivity list to kick off a process at certain times (maybe to write to a file or something), but thats probably a more advanced topic for now.
 

Code: 
library ieee;
use ieee.numeric_bit.all;
signal count: unsigned (3 downto 0);
process
begin
 wait until clk = '1';
 if reset = '1' then
 count <= "0000";
 else
 count <= count + "0001";
 end if;
end process;


in the above program since their is process statement so does the instructions within the process execute sequentially , i mean one after another ?


Code: 
begin
process
begin

a<='1';

b<='2';

end process


in the 2nd program does the instruction a<='1' is executed first and then b<='2' ? if the process statement would not be there then both the statements will be executed parallely ? am i right ?

- - - Updated - - -

Code: 
library ieee;
use ieee.numeric_bit.all;
signal count: unsigned (3 downto 0);
process
begin
 wait until clk = '1';
 if reset = '1' then
 count <= "0000";
 else
 count <= count + "0001";
 end if;
end process;


in the above program since their is process statement so do the instructions within the process execute sequentially , i mean one after another ?


Code: 
begin
process
begin

a<='1';

b<='2';

end process


in the 2nd program does the instruction a<='1' is executed first and then b<='2' ? if the process statement would not be there then both the statements will be executed parallely ? am i right ?
 

You need to understand how VHDL code maps to hardware. The code is not "executed" in the hardware. It is translated to hardware, and you need to understand this translation.
The sequential "execution" in a process is just a description of a single "event" in the hardware. If you assign values to two different signals, the order doesn't matter.
In the hardware they will be updated simultaneously.

For synthesizeable VHDL code, you should be able to draw the corresponding schematic. If you can't visualize the schematic, your VHDL code will be terrible.
It could be easier to go the other way. Find VHDL descriptions of standard hardware components, and try to understand the mapping.
 
ok, that means

Code: 
begin
process
begin

a <= '1'; 

a <='0';

end process ;

in this case firstly a is updated with 1 and then with 0 . right , since it involves a single event .


now another question is that if we connect an led corresponding to 'a' port then will it first glow and then goes off, or remains off . if i see from hardware prospective , then it depends on the propagation delay. now if the change from 1 to 0 occurs before the propagation delay then the the effect for a<='1' will not be seen.
 

@p11, this process has no wait or sensitivity list. It is not a good design. However, the a <= '0' statement will always be last, so a <= '0' will always be the result.
 

Code: 
begin
process
begin

a <= '1'; 

wait for 10 ns ;
a <='0';

end process ;



now it will get a value of 1 , and then 0 after 10 ns right. but we will not be able to see the difference , because of this short delay , to make the led to get on and off we either need to increase the delay or has to provide a clck such tht or its rising edge only , it switches from on to off and vice versa . am i correct ?
 

p11 said:
Code: 
begin
process
begin

a <= '1'; 

wait for 10 ns ;
a <='0';

end process ;



now it will get a value of 1 , and then 0 after 10 ns right. but we will not be able to see the difference , because of this short delay , to make the led to get on and off we either need to increase the delay or has to provide a clck such tht or its rising edge only , it switches from on to off and vice versa . am i correct ?
Click to expand...

Actually no - in this case it will be always '1', because there is no wait statement after the assignment to '0', so a is never set to '0'.
Processes are just loops that loop forever. No signal assignment occurs until a process suspends due to hitting a wait statement or getting to the end of the process if you have a sensitivity list.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
after the execution of wait for 10 ns , the next instruction will be executed then the process again repeats , so doesnot a act like a multivibrator of 10 ns delay between on and off state .. plz explain me , if possible with a very short example...
 

like I said, you would need another wait statement after the a <= '0' assignment
 

ok , i have got it . but wait statement is not synthesizable so , when i want to implement the program in fpga , then what do i need to do for a signal assignment .
 

when i want to implement the program in fpga , then what do i need to do for a signal assignment .
Click to expand...
Just assign them without a wait statement...
 

p11 said:
ok , i have got it . but wait statement is not synthesizable so , when i want to implement the program in fpga , then what do i need to do for a signal assignment .
Click to expand...

If you want to involve time, you need a clock and a clocked process.
This is hardware design. Draw a circuit diagram. Then we can discuss how to describe it in VHDL.
 

p11 said:
ok , i have got it . but wait statement is not synthesizable so , when i want to implement the program in fpga , then what do i need to do for a signal assignment .
Click to expand...

FPGAs don't run programs, get that straight now. i.e. STOP WRITING PROGRAMS FOR FPGAs!

FPGAs implement a hardware design that is developed by writing HDL code, which is a description of the logic.

If you want to have a delayed signal then you have to physically delay it. Either combinationally, by running it through multiple instantiated LUTs, or synchronously, by creating a circuit that uses a clock to delay the signal through multiple registers. The combinational method will have no method to create an accurate time delay as the delay is dependent on PVT. In your case with a 10 ns delay it should be done using a 100 MHz clock with all signals being synchronous to that clock. If do it synchronously then the delay will always be 10 ns as long as the clock is 100 MHz.
 

so that means either a signal assignment occurs only when all the statements in the process get executed (when there is sensitivity list) or if it gets a wait sttement (when there is no sensitivity list ).

Code: 
begin
process
begin

a <= '1'; 

wait for 10 ns ;
a <='0';
 wait for 10 ns ;
end process ;




now in the above example since there is no sensitivity list so wait statement is needed . but wait is not synthesizable so by writing a delay , in place of wait statements we can assign a signal.


Code: 
begin
process
begin

a <= '1'; 



 var := 5000;
while var >0 loop 
 var := var-1;
 end loop;


a <= '0'; 



 var := 5000;
while var >0 loop 
 var := var-1;
 end loop;


end process ;

so here a will behave like a clock with the delay as provided between on and off state . i hope now atleast am correct .......
 

p11 said:
so that means either a signal assignment occurs only when all the statements in the process get executed (when there is sensitivity list) or if it gets a wait sttement (when there is no sensitivity list ).

Code: 
begin
process
begin

a <= '1'; 

wait for 10 ns ;
a <='0';
 wait for 10 ns ;
end process ;




now in the above example since there is no sensitivity list so wait statement is needed . but wait is not synthesizable so by writing a delay , in place of wait statements we can assign a signal.


Code: 
begin
process
begin

a <= '1'; 



 var := 5000;
while var >0 loop 
 var := var-1;
 end loop;


a <= '0'; 



 var := 5000;
while var >0 loop 
 var := var-1;
 end loop;


end process ;

so here a will behave like a clock with the delay as provided between on and off state . i hope now atleast am correct .......
Click to expand...

STOP PROGRAMMING!
(i.e. don't use variables, don't use for loops, don't use while loops, don't use wait, don't use after delays....)

You need to come up with a schematic of the circuit before you write any code.

If you don't know how to design a circuit then you shouldn't be writing anything in VHDL. If all you know how to do is write software then you could use a high level synthesis (HLS) tool to write your "program" in C and hope for the best when the tool tries to translate that code into something the vendors tools understand and can synthesize, place, and route.
 

is process statement without sensitivity list synthesizable? if no then fine . but if yes then then how ??


Code: 
begin
process
begin

a<='1';
wait for 10 ns;

a<='0';

wait for 10 ns;
end process;
how to make the above code synthesizable. am asking this bec anywhere i read , i am getting that wait statement is not synthesizable. so if i remove the wait statement then no value will be assigned to the process as wait is needed after a signal assignment in this type of cases(without sensitivity list ). so what to do??
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top