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why not series pip cap?

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rightmederek

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Hi all,

I never see any ic using series pip cap, why is that?

Thanks,
DD
 

You need a dual poly process and this is not that common,
it used to be a way to go in mixed signal CMOS but I think
people have moved to MIM caps as better Q and more
latitude in placement can be had (e.g. poly cap means
no CMOS structures coincide, while a higher-layers MIM
can be placed over active devices if planarity is good).
POP / PIP caps also have higher series resistance / lower
Q, and have higher parasitic C on the bottom plate owing
to proximity to the substrate plane.
 

You need a dual poly process and this is not that common,
it used to be a way to go in mixed signal CMOS but I think
people have moved to MIM caps as better Q and more
latitude in placement can be had (e.g. poly cap means
no CMOS structures coincide, while a higher-layers MIM
can be placed over active devices if planarity is good).
POP / PIP caps also have higher series resistance / lower
Q, and have higher parasitic C on the bottom plate owing
to proximity to the substrate plane.

thanks, but is using it in series possible?
 

... is using it in series possible?

Actually, yes, with double poly PIP this should be possible. But only for achieving an even lower cap value than you would get with a single min. PIP structure (and why would you need such a small cap?). In such case use a symmetrical serialization, i.e. (P1-P2)---(P1-P2), to avoid parasitic asymmetries.

But do not use this concept to achieve high voltage caps! Voltage between P1 & substrate is limited, s. max. FOX (field oxide) voltage.
 

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