Implement look up table in Verilog in FPGA using xilinx devi

verilog lookup table

To implement a look up table for such as a multiplier, beside using a two dimentional array such as

reg [10:0] mem_arry[15:0]

and then initialize them in the "initial" block to the value you want?

Is there any other way of doing this?

I know that in VHDL, use can use two dimentional constant to implement a ROM look up table.

Besides using two dimentional array reg, and initialize in "initial" block, can someone recommend a different way?

verilog lut

Which Verilog compiler are you using? Which Xilinx chip? Do you want to initialize block RAM or distributed RAM?

XST does not support the Verilog "initial" statement, so I have to use the agonizing "// synthesis attribute INIT_xx ..." syntax.

Even worse, ModelSim ignores those attributes, so I have to duplicate the whole thing using "defparam myrom.INIT_xx ..." syntax, and then surround that with "// synthesis translate_off" controls so XST won't explode. Aargh!

verilog look up table

My method to implement LUT-ROM is by using the matlab to print out the
the whole module in a single file like below:

module lut
(
in,
out,
);

input [7:0] in;
output [7:0] out;

reg [7:0] out;

always @(in)
begin
case(in)
0: out =
1: out =

endcase
end

endmodule

You can use other script language to do the same work.

jarodz method is the most generic for sure and will get to the right result.

Alternatively, you can instantiate platform specific elements. For example, on my spartan3, I have LUT4, ROM256X1, and so on.


// LUT4: 4-input Look-Up Table with general output
// Spartan-3E
// Xilinx HDL Libraries Guide, version 12.1
LUT4 #(
.INIT(16’h0000) // Specify LUT Contents
) LUT4_inst (
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2), // LUT input
.I3(I3) // LUT input
);
// End of LUT4_inst instantiation


// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM
// Spartan-3E
// Xilinx HDL Libraries Guide, version 12.1
ROM256X1 #(
.INIT(256’h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
) ROM256X1_inst (
.O(O), // ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4), // ROM address[4]
.A5(A5), // ROM address[5]
.A6(A6), // ROM address[6]
.A7(A7) // ROM address[7]
);
// End of ROM256X1_inst instantiation


Regards

Richard

Can you tell me how to implement look up table for Sbox in aes? it requires 256 elements each of 8 bits.

Re: verilog lookup table

Check https://myfpgablog.blogspot.com/2011/12/memory-initialization-methods.html

IamElectric said:

To implement a look up table for such as a multiplier, beside using a two dimentional array such as

reg [10:0] mem_arry[15:0]

and then initialize them in the "initial" block to the value you want?

Is there any other way of doing this?

I know that in VHDL, use can use two dimentional constant to implement a ROM look up table.

Besides using two dimentional array reg, and initialize in "initial" block, can someone recommend a different way?

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