dpaul
Advanced Member level 5
My design has Verilog and VHDL modules along with Xilinx primitives.There are no problems with the Xilinx Verilog libs. I have also compiled all the Xilinx VHDL libraries (a dir has been created with the compiled libs and I also have an error free log file. I had used the Xilinx command COMPXLIB for compilation of the Xilinx VHDL libraries).
compxlib -s vcs -p /home/shared/Synopsys/I-2014.03-SP1/bin/ -arch spartan6 -dir /home/dpaul/rtl_work/xilinx_vhdl_libs -l vhdl -lib all -log /home/dpaul/rtl_work/xilinx_vhdl_libs_compile.log
Now while compiling using VCS of Synopsys, to compile the VHDL design files I used the following command:
vhdlan -full64 -work xilinx_vhdl_libs -f filelist_te0630_vhdl.txt
(I was of the opinion than in the vhdlan command using the -work switch and specfying the path where VHDL compiled libraries are located would solve the problem.)
But the VCS compiler gives me the following error (only error present) :
How can I fix this error?
In my /rtl_work dir, which is my VCS compilation dir, I can see the synopsys_sim.setup file being created. (file is attached)
- - - Updated - - -
Might be useful to know:
With no other error except that the one mentioned above, VCS successfully compiles the entire design. I can launch my simulations using ./simv -gui and view waveforms. But why such such an error exist is my fundamental question?
compxlib -s vcs -p /home/shared/Synopsys/I-2014.03-SP1/bin/ -arch spartan6 -dir /home/dpaul/rtl_work/xilinx_vhdl_libs -l vhdl -lib all -log /home/dpaul/rtl_work/xilinx_vhdl_libs_compile.log
Code:
dpaul@crest:~/rtl_work$ cd xilinx_vhdl_libs/
dpaul@crest:~/rtl_work/xilinx_vhdl_libs$ ll
insgesamt 56
drwxrwx--- 428 dpaul dpaul 20480 Apr 21 15:14 edk
drwxrwx--- 3 dpaul dpaul 4096 Apr 21 14:59 secureip
drwxrwx--- 3 dpaul dpaul 4096 Apr 21 15:00 simprim
drwxrwx--- 3 dpaul dpaul 4096 Apr 21 15:00 simprims_ver
drwxrwx--- 3 dpaul dpaul 4096 Apr 21 14:59 unimacro
drwxrwx--- 3 dpaul dpaul 4096 Apr 21 14:59 unimacro_ver
drwxrwx--- 3 dpaul dpaul 4096 Apr 21 14:59 unisim
drwxrwx--- 3 dpaul dpaul 4096 Apr 21 14:59 unisims_ver
drwxrwx--- 3 dpaul dpaul 4096 Apr 21 15:01 xilinxcorelib
drwxrwx--- 3 dpaul dpaul 4096 Apr 21 15:01 xilinxcorelib_ver
dpaul@crest:~/rtl_work/xilinx_vhdl_libs$Now while compiling using VCS of Synopsys, to compile the VHDL design files I used the following command:
vhdlan -full64 -work xilinx_vhdl_libs -f filelist_te0630_vhdl.txt
(I was of the opinion than in the vhdlan command using the -work switch and specfying the path where VHDL compiled libraries are located would solve the problem.)
But the VCS compiler gives me the following error (only error present) :
Code:
Error-[VHDLNOWORK] Missing library mapping
Logical library name 'XILINX_VHDL_LIBS' is not mapped to a physical
directory.
The show_setup command shows all of the mappings for the libraries. Please
use this command to validate that the named library above is mapped to a
physical directory in your synopsys_sim.setup file.How can I fix this error?
In my /rtl_work dir, which is my VCS compilation dir, I can see the synopsys_sim.setup file being created. (file is attached)
- - - Updated - - -
Might be useful to know:
With no other error except that the one mentioned above, VCS successfully compiles the entire design. I can launch my simulations using ./simv -gui and view waveforms. But why such such an error exist is my fundamental question?
Last edited:
