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Parsing Syntax error in conformal LEC

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Richa Verma

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Hi

I am getting following error while performing LEC with Cadence conformal.

Error: PARSE_ERROR: Parsing syntax error
// Missing a left parenthesis in an instantiation statement

The line of code for which this error is shown is :
Code: 
localparam                     MC_AUXM          = (MC_AUX == 0) ? 1 : MC_AUX ;

NOTE: before giving error, conformal showed following warning.

Identifier 'localparam' is a Verilog 2001 keyword

Code is compiled correctly with ncsim and did not show any syntax error also, after reviewing code throughly I do not find any need to add parenthesis.

Thanks in Advance!
Richa
 

Could you post whole RTL code and also LEC command you use to compile file? Standalone code seems to look fine.
 

Hi kornukhin
kornukhin said:
Could you post whole RTL code and also LEC command you use to compile file? Standalone code seems to look fine.
Click to expand...

LEC command to compile file and do file:
Code: 
bsub -Is -q long -P pictus /sw/cadence/conformal/111usr1/lnx86/bin/lec_64 -lpgxl -nogui -dofile rtc.do

//****************************************************//
// do file : conformal command script
//****************************************************//

// set log file
set log file lec.log -replace

// read golden file which which revised file needs to be compared
read design -verilog -gold -f file_list_old_rgm  

// read revised file
read design -verilog -rev -f file_list_rgm 


// set LEC mode
// Conformal has two operating modes//
// 1 : Setup mode //
// 2 : LEC mode //
set sys mode lec

report unmapped points

add compare points -all
compare

report compare data

exit

RTL code:
Code: 
  localparam                     MC_AUXM          = (MC_AUX == 0) ? 1 : MC_AUX ;
  parameter   [(16*MC_AUXM)-1:0] AUXCLK_SRC_AVAIL = {MC_AUXM{16'hffff}} ;
  parameter   [(24*MC_AUXM)-1:0] MC_ADIV_WIDTH    = {MC_AUXM{24'h444444}} ;
  parameter   [(24*MC_AUXM)-1:0] MC_AFRA_WIDTH    = {MC_AUXM{24'haaaaaa}} ;
  parameter    [(6*MC_AUXM)-1:0] MC_ADIV_DEF_EN   = {MC_AUXM{6'h3f}} ;
  parameter   [(78*MC_AUXM)-1:0] MC_ADIV_DEF_DIV  = {MC_AUXM{78'b0}} ;
  parameter    [(6*MC_AUXM)-1:0] MC_ADIV_DE_RO    = {MC_AUXM{6'h00}} ;
  parameter        [MC_AUXM-1:0] MC_ADIV_ALIGN    = {MC_AUXM{1'b0}} ;
        
  parameter                      MC_PCS_PRECISION = 20 ;
  parameter                [0:0] MC_AXBS_HALT_EN = 1'b0;
  
  localparam                     SIMPLE_CLK_MUX = 2'b00;
  localparam                      MC_SDIV_TRIGR_EN = 1'b1 ; 
  localparam        [MC_AUXM-1:0] MC_ADIV_TRIGR_EN = {MC_AUXM{1'b1}} ;

To debug, I commented the first localparam and re-ran the LEC. But, the same error popped up for next localparam.
 

"Identifier 'localparam' is a Verilog 2001 keyword" should tell you what the problem is. Try:

read design -verilog2k

Instead of:

read design -verilog
 

If read design -verilog2k doesn't solve the problem, just read the Conformal User Reference manual (it is just 15 min work). There you'll get a variety of options and choose the right one.
 

jbeniston said:
"Identifier 'localparam' is a Verilog 2001 keyword" should tell you what the problem is. Try:

read design -verilog2k

Instead of:

read design -verilog
Click to expand...

Thanks jbeniston
This solved my problem! :)
 

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