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TSMC 0.18um process flow description

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ibm cmos 7rf process

Dear All,

I am doing TSMC 0.18um layout. I think it would be nice if I can have the detailed description of the process flow, so I can visualize it when I am drawing. What I can find is a very brief description of the process flow with a lot of abbreviations, it is very frustrating to figure out the process from it.

Can anyone help?
 

Hello,
I have similar request for 0.18 um IBM CMOS 7RF process. Any help will be highly appreciated.
 

I posted this some time ago but do not know how to point back to a previous post. Not sure if this is what you are asking for and it does not include the back end metallisation which is easy to visualise.
 

Excellent doc!
Could you post a backend portion of it as well?

Added after 2 hours 18 minutes:

Upon a closer examination, the doc does not mention halo implant stage. Is it really 0.18um flow?
 
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