Two questions in cadence virtuoso (gnda , parasitic reduction)

Hello
Dear all,
I have two questions , kindly help me about them
1- What is gnda (different from gnd in AnalogLib ) is used for what is the difference between it and gnd and why if used instead of gnd it gives me errors ?

2- While I am reading in user guide for ADE I found that there are parasitic reduction options in ADE !
How can simulation help me to reduce parasitics although parasitics is something depend on my design and the transistor width and distance between them and other wires/pins (i.e depend mainly on my design and tech file ) how can reduction could happen ????

Your help is really appreciated


Best Regards,
Mahmoud

Hi,
1 : gnda is an arbitrary net name. In spectre you HAVE TO connect it to gnd (which is the compulsory 0V reference for calculations).
You can use agnd it to have different current return path in your ASIC (ie one from low noise analog front end : agnd , one for analog gnd, one for digital dgnd..., thus ensuring good EMC). Of course, outside your ASIC, all gnd are tied together (or not, but that is another long story...).
2 : parasitic reduction will not reduce parasitics in your layout, but filters the netlist and remove small (below a threshold) serial resistor and capacitor, thus reducind the number of node in the netlist, thus decreasing simulation time.

Hope this helps !
Regards,
RG

gag2000 said:

Hi,
1 : gnda is an arbitrary net name. In spectre you HAVE TO connect it to gnd (which is the compulsory 0V reference for calculations).
You can use agnd it to have different current return path in your ASIC (ie one from low noise analog front end : agnd , one for analog gnd, one for digital dgnd..., thus ensuring good EMC). Of course, outside your ASIC, all gnd are tied together (or not, but that is another long story...).
2 : parasitic reduction will not reduce parasitics in your layout, but filters the netlist and remove small (below a threshold) serial resistor and capacitor, thus reducind the number of node in the netlist, thus decreasing simulation time.

Hope this helps !
Regards,
RG

Click to expand...

Thanks a lot for your interest, really appreciated

but I can't get the answer fully for the first one
1- how to have different current return path in ASIC , and if in the real physical world all of them connected in groun what makes different in simulation and how it will help me if I did like that ?

Re: gnda connection

MahmoudHassan said:

1- how to have different current return path in ASIC , and if in the real physical world all of them connected in groun what makes different in simulation and how it will help me if I did like that ?

Click to expand...

As gag2000 told above,

you HAVE TO connect it to gnd ...

Click to expand...

You can do this e.g.

a) by a DC vsource with 0V
b) via a 0Ω resistor

You can also use a very low ohmic resistor (perhaps in series with an inductor) if you want to analyse the influence of the ground supply's impedance.

Same could be done for the positive supply rail(s), of course.

Re: gnda connection

erikl said:

As gag2000 told above, You can do this e.g.

a) by a DC vsource with 0V
b) via a 0Ω resistor

You can also use a very low ohmic resistor (perhaps in series with an inductor) if you want to analyse the influence of the ground supply's impedance.

Same could be done for the positive supply rail(s), of course.

Click to expand...

Thanks a lot for your help , but till now I don't understand why we are using it gnda (I know it is should be connected to ground ) but why I am using it ? and when I need to use it ?

Thanks a lot for your interest

Re: gnda connection

MahmoudHassan said:

I don't understand why we are using .. gnda (I know it is should be connected to ground ) but why I am using it ? and when I need to use it ?

Click to expand...

On a mixed digital/analog chip you may want to separate digital GND and analog GND from each other - as long and as good as possible. Digital circuits switch currents and so generate voltage drop spikes on their GND connections, whereas analog circuits may be sensitive to such voltage spikes. So you try and keep these GND connections separated from each other, call them e.g. dgnd and agnd, and connect them only at their common GND pad.

Of course usually all gnd connections are on the same substrate (bulk p-substrate assumed), but if their metal gnd connections have lower resistance than their gnd connection via substrate, most of the current flowing to the GND flows via the metal connections, so their voltage drop can be separated until their connection at the common pad.