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Subthreshold Opamp Design in 32nm

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IntuitiveAnalog

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Hi All,
I am designing a two stage miller opamp (pmos input differential pair) in subthreshold region. I am using 32nm technology node. The parameters are given below:
1. Supply voltage = 1V
2. Bias Current = 200nA
3. Transistor Length = 160nm=(5 Lmin)
There are no specific requirements but I have to just reduce power dissipation.
I am getting all the responses quite correct but in transient analysis the output dc level is not the same as input dc level.
I will be very much thankful if anyone could figure out how to make input and output dc level same.




Thanks
 

This 1mV offset is caused by finite open loop gain. For source follower \[V_{out}=V_{in}/(1+K^{-1})\]
 

First of All thanks Dominik for reply.
I simulated two stage opamp design given in Allen Holberg's book but there was no offset(The design of course was having higher gain around 80 dB).
 

One more thing which I observed is that for 2mVp-p input signal the output swing is 1.7mVp-p in unity gain inverting configuration.
I will be very much thankful if anybody could figure out what could be the reason behind this attenuation.
Thanks
 

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