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Footprint design at PCB editor - DRC error

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yolco

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Hi,

I'm just trying to design the footprint for a QFN Component.

The pins, thermal pad, vias, oard geometry, package, etc are already placed, but when thermal pad is placed over the vias (which is the right place for them), DRC error 'SMD Pin to Thru Via Spacing' is shown in every via.

If I show the element the message is:
< DRC ERROR >

Class: DRC ERROR CLASS
Subclass: TOP
Origin xy: (-2.450 -2.450)
Constraint: SMD Pin to Thru Via Spacing
Constraint Set: DEFAULT
Constraint Type: NET SPACING CONSTRAINTS

Constraint value: 0.1 MM
Actual value: OVERLAP

- - - - - - - - - - - - - - - - - - - -
Element type: STAND-ALONE PIN
Class: PIN

(0.000 0.000)

- - - - - - - - - - - - - - - - - - - -
Element type: VIA
Class: VIA CLASS

origin-xy: (-2.450 -2.450)

not on a net
Number of connections: 0

Padstack name: Component_VIA
Type: Through Plated
Circle_drill : 0.200

padstack defined from TOP to BOTTOM
rotation: 0.000 degrees
Via is not mirrored
Click to expand...

Could someone help me to solve the issue, please?
Also, it would be helpful an explanation about it to understand it in a better way.

KR!
 

hi,
open contraint manager(short cut is ALT+E+N).in this contraint manager select the analyze mode-->analysis mode-->select SMD Pin mode.choose via at SMD pin for choose ON mode.
 

Hi,

Ok, issue solved.

The reasons was:
- Wrong thermal pad design.

I changed the thermal pad for a shaped which works as a static copper area, and DRC errors have removed.

Thanks.
 

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