Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

NBTI phenomena in simulators such as Spectere

Status
Not open for further replies.

electronics20

Full Member level 1
Joined
Apr 27, 2011
Messages
99
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
1,888
Dear researchers and students
I dealt with a mediocre question in regard to NBTI phenomena in simulators such as Spectere. Is NBTI issue taken into account in the said simulators spontaneously by Spectere, for example in 40nm TSMC technology, or we have to apply this phenomena to the circuit?
Many thanks
Best,
 

Hi, Every foundry units research on reliability phenomenons like NBTI before developing suitable models. Hence I believe that doing corner analysis and Monte Carlo simulations would take care of NBTI effects as well. It may not be included in Typical performace models of MOSFETs. Thanks.
 
... Is NBTI issue taken into account in the said simulators spontaneously by Spectere, for example in 40nm TSMC technology, or we have to apply this phenomena to the circuit?

This depends on the models which you get from the fab/foundry: if they include the NBTI-important parameters in their BSIM3 or BSIM4 model files.

The reactions on NBTI phenomenon you probably won't see from "standard" analysis setUps, because NBTI needs a long-time observation. Like with real NBTI measurements on silicon, you will need a testBench for accelerated NBTI effect, i.e. simulation under high current / high temperature conditions.
 
Cadence Virtuoso using RelXpert tool for reliability simulations. In ADE L You can find it in menu→simulation→reliability.

Unfortunately I nvere used it, I have an info only from 4 chapter of this book
 
All of the modeling I have done, or seen done, has always
been on virgin devices. I have yet to encounter a model
set which includes aging, even as a corner. Rather, the
norm has been to constrain allowable drifts in qualification
and make the process guys hold up their end if qual fails.

But I gather this is not the norm in commercial sacrifice-
anything-but-the-pennies-per-part product development,
DSM foundries would rather it be your problem than theirs.

So good luck with that.
 

In Spectre or Spice you model your circuit, then you need to add ageing parameters, for NBTI for example, to your model. This can be simulated by reliability tools such as MOSRA (Synopsys) and RelXpert (Cadence) afterwards.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top