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[SOLVED] cadence drc error GR131_ana

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Hi all,

I am designing an inverter on cadence, now I have an error I can not solve, please help me...
(Gates not over TG) NOT covered by GRLOGIC) OR ((Gates not over TG) under QT MIM capacitor), must have a RX tiedown by M1 metal

Thank you!

Leon
 

Hi,
You are facing problems with your layout design.
DRC- Design Check Rule .
So, there are issues with your design..You haven't placed the gates well.
Also, Keep in mind the lambda rules while making layouts.

A inverter in Microwind should look something like this :
inverter.png
 

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