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Xilinx Coregen initialization of ROM

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Tapojyoti Mandal

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I have created a ROM using distribute memory generator of COREgen and during the creation initiated it with a .coe file. But now i want to change the initialization of the ROM by changing the .coe file but i am unable to do it.
I have tried changing the .coe file when asked after double clicking on the .xco file of ROM.But still the initialization of the ROM remains same.
How to change the .coe file for the ROM?
 

If you change the .coe file and then recompile the IP in Coregen, it should work. How are you simulating? Are you sure your simulation is pointing at the NEW files that coregen created. Maybe you never updated the simulation files (I've done that).
 
barry said:
If you change the .coe file and then recompile the IP in Coregen, it should work. How are you simulating? Are you sure your simulation is pointing at the NEW files that coregen created. Maybe you never updated the simulation files (I've done that).
Click to expand...
Thanks for the suggestion.Yes, I observed that rewriting the .coe file then regenerating the core leads to the new initialization vectors being used to simulate.

But i was wondering that is there any other method to update the initialization of rom. Every time i want to implement with new initialization bit vector,I am using SPIM to get the Machine code from assembly program, then copy and paste it to the .coe file , then regenrate the core , and implement my complete system (including the coregen ROM) to generate the bitgen file to implement on FPGA.
Is there any other method for updating?
 

Tapojyoti Mandal said:
Thanks for the suggestion.Yes, I observed that rewriting the .coe file then regenerating the core leads to the new initialization vectors being used to simulate.

But i was wondering that is there any other method to update the initialization of rom. Every time i want to implement with new initialization bit vector,I am using SPIM to get the Machine code from assembly program, then copy and paste it to the .coe file , then regenrate the core , and implement my complete system (including the coregen ROM) to generate the bitgen file to implement on FPGA.
Is there any other method for updating?
Click to expand...

That's completely not what you asked.
 

barry said:
That's completely not what you asked.
Click to expand...

No, you already answered my question on the 2nd post and it solved my problem.
I was just asking if there is any other alternative to this methodology.I also got the answer to that as provided by "ads-ee"
 

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