kart339
Junior Member level 2
Hello ppl,
I am designing a combinational logic block of which a 6 bit divider is an important part. I came across this issue when I coded the divider in Verilog. Here is the code...
always @(posedge clk) begin
if (rst) Div_Out=0;
else if (highz) Div_Out=6'bz;
else Div_Out=IN1/IN2;
end //end always
testbench:
IN1=6'd4;
IN2=6'd5;
I get the solution as 0 and for those cases when IN1 > IN2, I get 1. I am supposed to get a fractional number (like 0.5, 0.6...etc) as the result for use in my next block. I temporaritly resolved this issue by using
Div_Out=IN1*10/IN2
I get my result as 8 for 0.8 which I can still use.(as it is logic)
But as is obvious I will get hit on my area as well as power if I use that 6 bit multiplier! Is there a better solution that someone knows......please share your info. Will be highly grateful!
Thanks everyone!
Kart
I am designing a combinational logic block of which a 6 bit divider is an important part. I came across this issue when I coded the divider in Verilog. Here is the code...
always @(posedge clk) begin
if (rst) Div_Out=0;
else if (highz) Div_Out=6'bz;
else Div_Out=IN1/IN2;
end //end always
testbench:
IN1=6'd4;
IN2=6'd5;
I get the solution as 0 and for those cases when IN1 > IN2, I get 1. I am supposed to get a fractional number (like 0.5, 0.6...etc) as the result for use in my next block. I temporaritly resolved this issue by using
Div_Out=IN1*10/IN2
I get my result as 8 for 0.8 which I can still use.(as it is logic)
But as is obvious I will get hit on my area as well as power if I use that 6 bit multiplier! Is there a better solution that someone knows......please share your info. Will be highly grateful!
Thanks everyone!
Kart