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I think LT2 & VT2 are equally relevant for latchup as LT1 & VT1 are (actually more relevant as they are closer, and so their collector-to-base series resistance in substrate should be lower).
But for the latchup explanation, the connection between (any) two such transistors is sufficient, I guess.
In the cartoon as drawn, the closer-coupled PNP and NPN
will determine the latchup onset owing to their lowest
series resistance to each other and their highest shunt
resistance to the "taps" (ties). After the first 4-layer
device fires, you are done. This is where "negligible"
comes from.
Now this cartoon represents some worst layout practices
(in respect to latchup suppression). But in the commercial
arena you concern yourself with "good enough" and moving
in a timely way to the next problem. If shoddy is good
enough then shoddy will probably be what is done.
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