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Simple board Xilinx to turn on some led's

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Vlad.

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Hello, I made a schematic inspired from a board from Digilent. The board that I have designed use xilinx Kintex 7 XC7K70T-1FBG484C. What I want from you is to tell me is the schematic is correct and if is something wrong please tell me. I not sure if i need to use the second crystal resonator (50MHz) called in my schematic EMCCLK, because i don't have external memory for fpga. The setup is simple some led's, buttons, fpga, jtag conector, crystals resonator. Thank you verry much,
Regards.
 

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  • fpga project v2.pdf
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Vlad. said:
Hello, I made a schematic inspired from a board from Digilent.
Click to expand...
Doesn't look like you started with the Digilent design and removed what you didn't want/need.

Vlad said:
The board that I have designed use xilinx Kintex 7 XC7K70T-1FBG484C. What I want from you is to tell me is the schematic is correct and if is something wrong please tell me. I not sure if i need to use the second crystal resonator (50MHz) called in my schematic EMCCLK, because i don't have external memory for fpga. The setup is simple some led's, buttons, fpga, jtag conector, crystals resonator.
Click to expand...
The 200 MHz differential was the clock that was likely for a DDR memory as it would likely have better jitter specs. The single ended 50 MHz was probably used as the general purpose clock, at least that is what I've seem on most of the Digilent, Avnet, and Xilinx boards I've used.

About the schematic, you've got a lot of missing stuff, and the bypass caps you are using look wrong. There are recommended bypass capacitors for all the voltage rails in the following document. Look at Table 2-2 on page 15 and find the device you are using. Xilinx package substrates have a lot of high frequency bypass caps already, so you don't need so many capacitors on the board.

I noticed you didn't even select a programming mode or a device to hold the configuration bitsteam. You also have the P and N of the differential clock swapped (though that won't necessarily cause any problems).

I hope you realize that building something like this should be done using a multilayer board not just a 2 sided home made board. Part of the supply high frequency bypass capacitance is the existence of a good ground/power plane pair, which can't be readily done at home, using two-sided hobby stuff.

I very strongly suggest you not build this board, but just buy a Digilent, Avnet, Xilinx board. It's apparent you haven't designed a board like this before and designing your first board using a ~$160 part isn't a advised unless you've got money to burn.
 

Hello man, thank for replay. This board is a test board. I was requaired to make a board with this kind of fpga to run a basic test, without any chips on this board (memory, comunication or other chips). I don't need a memory nonvoltatile to keep the configuration, every time I power up the fpga i will program it via jtag header. The board was designed in 8 layers.
Please look here at page 6, at what they say about crystal resonators: http://www.digilentinc.com/data/products/netfpga-1g-cml/netfpga-1g-cml_rm_v3.pdf

Please tell if with what I say now to you the fpga will run. Thank you!
 
Last edited:

Set the M0-M2 pins to some value not just floating. Pick a mode that makes the FPGA slave serial or similar. You don't want the FPGA in master configuration mode.

Don't leave CCLK, DONE, INIT_B, and PROGRAM_B floating (probably also CSI_B and FCS_B).

Based on what you've stated...you don't even need the EMCCLK, JTAG does not use an external clock it uses TCK to drive the configuration, so EMCCLK is not even used.

DNI the R20 100 ohm or better yet remove it completely. The differential termination in the IO pad will be better than using an external resistor.

You still need to change the bypass capacitors, you have way more than necessary and a lot of them are not the recommended values. You may want to read the document in post #2 for PCB design for Xilinx parts.

You seem to be supplying power via some connector, make sure that there isn't some specific power sequencing required, especially if you happen to be using ES silicon.
 

CCLk, DONE, INIT_B and PROGRAM_B should i connect it hardware to ground via resistor or i can do it software? i will implementate the configuration of m0-m2 with jumpers so can i configure what i need later.
The power supply is anathoer board that i have with ADP5050 from analog devices, and about the capacitors i read you're sugestion and i will change that. Thank you
 
Last edited:

Vlad. said:
CCLk, DONE, INIT_B and PROGRAM_B should i connect it hardware to ground via resistor or i can do it software?
Click to expand...
Yes, No, No, and No. Can't do it in software. You should look over Table 2-2 on page 22 of UG470, which shows the required connections in JTAG (Only) mode. Also look at page 68 of UG470 for specific information on what to do with DONE, INIT_B, and PROGRAM_B (FYI, the ones with _B on the end are active low).

You really need to read the documentation (specifically UG470, UG471, UG472, UG476 (if using GTX), UG480 (if using XADC), and UG483) if you want to design an FPGA into a board unless you like to respin boards. ;-)
 

Hello man, thank you a lot for helping me, after i read you're document's I modify the schematic so:
CCLK- goes to ground via 1k resistor
DONE, INIT_B and PROGRAM_B goes to 3.3V via 1k resitor
Acording the jtag mode only this pins and pins from jtag are used, and i don't need the EMCCLK 50MHZ clock. So now you thing is correct? I will change the cap's at final.
And I not use ADC, GTX, all i want is to power up the FPGA and program it via jtag and turn on some led's via button's. is a setup test, to test the FPGA in a special enviorement. Sorry I can say more.
 

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  • fpga project v3.PDF
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Last edited:

Hello ads-ee, I have some question regarding the programming this FPGA, how can I contact you? You have am mail address? Thank you.
 

Vlad. said:
Hello ads-ee, I have some question regarding the programming this FPGA, how can I contact you? You have am mail address? Thank you.
Click to expand...

Use the forums, I'll overlook the request for help via email. And no PMs
 

Ok, I have a question for you....
The differential clock can be put on any MRCC pin and can be defined by software where to be bound? Because regarding to my schematic my differential clock is bound on R3 and R4 (are MRCC pins) and our software developer tell me that might be an error on this bounding.
 

Yeah it's wrong, sorry I didn't catch that earlier...Your board designer drew bad symbols for the FPGA.

Code: 
P4    IO_L[COLOR="#008000"]11[/COLOR]P_T1_SRCC_34        1          34    VCCAUX        HP
R4    IO_L[COLOR="#008000"]11[/COLOR]N_T1_SRCC_34        1          34    VCCAUX        HP
R3    IO_L[COLOR="#EE82EE"]12[/COLOR]P_T1_MRCC_34        1          34    VCCAUX        HP
T3    IO_L[COLOR="#EE82EE"]12[/COLOR]N_T1_MRCC_34        1          34    VCCAUX        HP
These are the relevant pins for the package you are using (https://www.xilinx.com/support/packagefiles/k7packages/xc7k70tfbg484pkg.txt). As you can see the R3 is the P side of L12 and the N side is on T3. R4 is part of IO pair L11.
 

Thank you, so if i bound Clock_N to R4 and and Clock_P to P4 should be ok. They must be part of same IO pair.
Corect me if i wrong.
 

That is correct.

One thing to note is the SRCC stands for Single Region Clock Capable, which means it can reach a regional clock buffer that only spans a single region (bank). The MRCC stands for Multiple Region Clock Capable, which means it can reach the bank it is in and I believe the adjacent regions above and below. Look over UG472 for details.
 

Ok, I really apreciate youre help.
Can be done by software to reverse N with P and P with N from input of clock? i just asking...
 

Vlad. said:
Ok, I really apreciate youre help.
Can be done by software to reverse N with P and P with N from input of clock? i just asking...
Click to expand...

VHDL/Verilog are not software, so I'm not sure if you are referring to those languages as software.

The answer is no, unless you mean adding an inversion to the RTL code (VHDL/Verilog) for the clock, which in the case of Kintex 7 can be implemented as a local inversion at the flip-flops or if you use an MMCM there are inverted output clocks.
 

Yes i understand, VHDL/Verilog is hardware language.
I reffer if I put the clock_N to an input P and clock_P to an input N of FPGA can be corrected by program, mean addding some inversion?
Can you tell me if I bound ok the led's and buttons? I will modify the schematic this weeken, then maybe you have time to see it..
 

Vlad. said:
I reffer if I put the clock_N to an input P and clock_P to an input N of FPGA can be corrected by program, mean addding some inversion?
Click to expand...
See post #15 above...Second paragraph about programmable inversion present at clock pins of the Flip-flops. You can find a reference to this in the UG474 on page 22 Control Signals.
 

Hello man, We have a software guy that make for us a bit file for this FPGA, but when i try to burn it in the fpga i get an error like this:
Code: 
Welcome to iMPACT
iMPACT Version: 14.4
Project: 'C:\Xilinx\14.4\ISE_DS\\auto_project.ipf' already exists.
Original project has been renamed to 'C:\Xilinx\14.4\ISE_DS\\auto_project_1.ipf'.
Project: C:\Xilinx\14.4\ISE_DS\\auto_project.ipf created.
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : setMode -bs
Enumerating cables. Please wait.
PROGRESS_START - Starting Operation.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
 Driver file xusb_xp2.sys found.
 Driver version: src=2301, dest=2301.
 Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS 14:14:44, version = 1021.
=======================================================
Found cable - > ESN = 000017DEA62701.
=======================================================
Connecting to cable (Usb Port - USB22).
Checking cable driver.
 Driver file xusb_xp2.sys found.
 Driver version: src=2301, dest=2301.
 Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS 14:14:44, version = 1021.
PROGRESS_END - End Operation.
Elapsed time =      3 sec.
INFO:iMPACT - Digilent Plugin: Plugin Version: 2.4.4
INFO:iMPACT - Digilent Plugin: no JTAG device was found.
// *** BATCH CMD : setCable -port usb21 -baud -1
Enumerating cables. Please wait.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
 Driver file xusb_xp2.sys found.
 Driver version: src=2301, dest=2301.
 Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS 14:14:44, version = 1021.
=======================================================
Found cable - > ESN = 000017DEA62701.
=======================================================
Connecting to cable (Usb Port - USB22).
Checking cable driver.
 Driver file xusb_xp2.sys found.
 Driver version: src=2301, dest=2301.
 Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS 14:14:44, version = 1021.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
 Driver file xusb_xp2.sys found.
 Driver version: src=2301, dest=2301.
 Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS 14:14:44, version = 1021.
 Cable PID = 0008.
 Max current requested during enumeration is 300 mA.
Type = 0x0005.
 Cable Type = 3, Revision = 0.
 Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 2401.
File version of C:/Xilinx/14.4/ISE_DS/ISE/data/xusb_xp2.hex = 2401.
Firmware hex file version = 2401.
PLD file version = 200Dh.
 PLD version = 200Dh.
Type = 0x0005.
ESN option: 000017DEA62701.
Attempting to identify devices in the boundary-scan chain configuration...
INFO:iMPACT - Current time: 3/25/2015 5:55:53 PM
// *** BATCH CMD : Identify -inferir 
PROGRESS_START - Starting Operation.
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc7k70t, Version : 0
INFO:iMPACT:1777 - 
Reading C:/Xilinx/14.4/ISE_DS/ISE/kintex7/data/xc7k70t.bsd...
INFO:iMPACT - Using CseAdapterBSDevice
INFO:iMPACT:501 - '1': Added Device xc7k70t successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
PROGRESS_END - End Operation.
Elapsed time =      0 sec.
// *** BATCH CMD : identifyMPM 
// *** BATCH CMD : assignFile -p 1 -file "C:/Users/Admin/Desktop/main.bit"
'1': Loading file 'C:/Users/Admin/Desktop/main.bit' ...
done.
INFO:iMPACT - Using CseAdapterBSDevice
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
but the original bitstream file remains unchanged.
UserID read from the bitstream file = 0xFFFFFFFF.
Data width read from the bitstream file = 1.
INFO:iMPACT:501 - '1': Added Device xc7k70t successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
INFO:iMPACT - Current time: 3/25/2015 5:56:11 PM
// *** BATCH CMD : Program -p 1 
PROGRESS_START - Starting Operation.
INFO:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File.
INFO:iMPACT:1578 - '1':  Device IDCODE :        00000111011001000111000110110111
INFO:iMPACT:1579 - '1': Expected IDCODE:    00000011011001000111000010010011
PROGRESS_END - End Operation.
Elapsed time =      0 sec.
Do you have any ideea what is the wrong?
 

The JTAG IDCODEs for the device and the bit file don't match.

Before you ask, no I don't know which is the correct IDCODE. There is a document somewhere on Xilinx.com (it might be in UG470) that has the IDCODEs for the devices. You might have a different device on the board than what is called out in the project.
 

The name of FPGA from hardware is the same with the name of FPGA from bit file, can the idcode be changed?
 

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