How to calculate gate overhead for scan?

I have a design with 20 -dff(d flops), 19 xnor and 18 nand gate, 15 inverters before scan insertion. after scan insertion i have 20 -sff (scan flops), 19 xnor and 18 nand gate, 15 inverters. now i want to know what is the gate overhead before and after scan insertion. how to calculate the gate overhead? when i was referring this i found a formula of gate overhead as : 4nsff/(ng+10nff) but im not sure how to calculate this exactly .As the explanation says 4 correspnds to 4 gates in mux present in scan flop. and 10 corresponds to 10 gates present in d flop.Now wht is ng that i need to take and how to get the incease of overhead before and after scan insertion? Can some body teach me this please. or is this wrong formula and there is soemthing else to be used?

10% is roughly the area increased from flop to scan flop.
but it could be worst if you std cell library has a limited number of cell.

I am not sure what is the purpose of the exercise... there is obviously an area overhead once you convert d-FFs to scan d-FFs. Most tools are able to handle scan flops from synthesis. Also you have to see if the flops have dedicated scan_out port. The tool will take care of the upsizing the gates to meet the timing, add scan buffers to meet the hold time, maybe change the logic of the Xor to be implemented with other gates etc etc....
if this is pure academic exercise then it is worth doing it.....else the scan methodology is tried and tested and there is nothing like overhear as it is a basic necessity.

We can report the area before doing scan insertion and after doing scan insertion. In synopsys tools, it is showing the gate overhead also.