Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
While I'm sure they're some books that overview the design-flow from gates -> GDSII, that's mostly theoretical because back-end design is set by a) Foundry and b) tool vendor. (Implementation of back-end varies from foundry to foundry, and from tool to tool.)
Hint: At 130nm or below, you must first ask your foundry if they even allow a COT-flow (customer owned tool.) Many fabs will recommend that you (the customer) handoff your synthesized gate-netlist and constraints-file to the foundry, and let the foundry complete the backend design.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
