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verilog code using combinational

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i want a verilog code for the following logic in post synthesis simulation

when e = 1, output = 1
when e = 0, output = 0
when e = x, output = 1

I have tried casex and many more things but nothing is working in post synthesis simulation.Anyone tell me a verilog code to get the following logic.If possible, try to avoid using registers.use more combinational.
 

The logic here is a bit confusing. In the condition e = x do you mean it as a don't care ? In that case if you write code using casex I believe you'll get only infer a tie high value since irrespective of e's value your output is always 1.

If this is not what you have in mind can you elaborate a bit more on your requirement?
 

It doesn't work because there is no such boolean operation.
 

Well the logic is simple...
input = 1, output = 1;
input = 0, output = 0;
input = x, output = 1;

I just want a synthesizable verilog code for this. When the condition on Don't care arises, then I want output to be 1...how can i write a synthesizable verilog code for this
 

You don't consider that 'x' is no physical signal state and can't be represented in hardware. What are you trying to achieve?

Input signals can be either '0' or '1', nothing else.
 

I'm not sure what you are trying to do here.

The x you see in simulation is different from a don't care. It means the signal value is unknown, i.e. there could be multiple drivers acting on your input (signal e) and hence the state of input (signal e) can't be resolved.

It's not same as a don't care.

So if you are seeing an x in your input during simulation that means there's some problem with the logic your wrote to drive the input. Please review your code and try again.
 

A "Don't care" or "X" for synthesis means the ignore the input when computing the output. You can't synthesize logic that both ignores the input and also looks at the input at the same time.

What you are asking would make more sense if there were two inputs

input1 = 1, input2 = 1, output = 1;
input1 = 1, input2 = 0, output = 0;
input1 = 0, input2 = x, output = 1;

That third line is saying we don;t care what the value of input2 is, so we could have written it as these two lines instead.

input1 = 0, input2 = 0, output = 1;
input1 = 0, input2 = 1, output = 1;

The synthesized logic for this would be

output = !(input1) || input2;
 

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