[SOLVED] Design is NOT on-the-fly during Partial Reconfiguration ! Why?

Hello everybody,

I did a partial reonfiguration using PlanAhead 14.7 and the vitfiles have been created. First, I downloaded the full configuration file into the FPGA and simultaneousl monitored the output pins (JA1, JA2 in Xilinx Gensys board including XC5VLX50T) PMOD connectors The show two ring oscillators while one of them is in static part and the other one is prtialy reconfigured.
Once I download the Partial bitfile for ring oscilator 2 via IMPACT, the signal of ring oscillator 1 fades, which means the design is stopped !!!!! I am extremely surprised why it happens??!! The concept of Partial Reconfiguration isthe static part remains on-the-fly but it is not !!!!
Can anybody help me with this issue??

Thank you all,

Given that on-the-fly partial reconfiguration is a feature that requires a license you would have to buy from Xilinx, you should discuss this problem with your Xilinx FAE. When I used this functionality a few years ago, the license also included a 2-day training course and lots of tech support from the FAE's.

Talking to them would definitely be your best bet, since you have really not given us enough information to even make an educated guess at what is wrong.

r.b.

rberek said:

Given that on-the-fly partial reconfiguration is a feature that requires a license you would have to buy from Xilinx, you should discuss this problem with your Xilinx FAE. When I used this functionality a few years ago, the license also included a 2-day training course and lots of tech support from the FAE's.

Talking to them would definitely be your best bet, since you have really not given us enough information to even make an educated guess at what is wrong.

r.b.

Click to expand...

Hello R.B.,
@Rberek
Thanks for your reply. The PlanAhead version that I am currently use is the licensed one. About the details of my design, I implemented two ring oscillator functioning slightly at a same frequency (about 2.5MHz) along with other control circvuits such as SEU controller, FIFO, RxTx module. All these module plus one of the ring oscillators belong to the Static part. The other remaining ring oscillator would be the unique reconfigurable module that is intended to be partially reconfigured. It is noticable that each ring oscillator is comprised of a delay line chain created by inverters implemented by LUTs.

Thank you so much,

msdarvishi said:

The PlanAhead version that I am currently use is the licensed one.

Click to expand...

Planahead isn't the same as partial reconfiguration. The license for PlanAhead isn't the license for partial reconfiguration, the partial reconfiguration license AFAIK was separate from any other license.

Regardless of the current licensing of partial reconfiguration are you sure you created a partial reconfiguration bit file and not some full bit file for the partial reconfiguration bitstream? The partial reconfiguration bitsteam should be significantly smaller and should have a different command header with different (most likely) frame address and length.

msdarvishi said:

All these module plus one of the ring oscillators belong to the Static part. The other remaining ring oscillator would be the unique reconfigurable module that is intended to be partially reconfigured. It is noticable that each ring oscillator is comprised of a delay line chain created by inverters implemented by LUTs.

Click to expand...

Can you attach a .zip archive with the complete project for this? That way we can do a quick check on ISE 14.7 to see if there is not some small mistake / miscommunication.

Hello,

Relying on the comment provided by @ads-ee, now the problem got SOLVED !! It's working very well.
The problem was that I had the following bit files:

config_1.bit
config_2.bit


once I was downloding config_2, since it was a FULL bitstream (nor a partial one) with the size of config_1 and it includes the frames of Static part as well, the design was being stopped because indeed I was doing a FULL recongifuration.

I search in PlanAhead.runs directory and I found the following bitfiles:[/COLOR]

config_1_ro_partial.bit
config_2_ro_partial.bit

These are the partial bit files with a very very smaller sizes compared to the config_1. Once I downloaded for example config_2_partial.bit into the FPGA I saw on the oscilloscope that the RO0 in the static part was on-the-fly while the RO1 was being reconfigured...

Thank you very much @ads-ee for your great hint

Solved problem, even better. :thumbsup: