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Polygon comparison would be done with a DRC script. I
have only seen this in user-added menu extensions
myself, with some CAD Dude having created the layer
by layer XOR code (you need it to follow all of the mask
generation Booleans as well as WYSIWYG polygon data,
down to the mask data level).
Connectivity comparisons can be done in Assura, you
simply use another extracted netlist from another layout
instead of a schematic extracted. But this does not give
a polygon equivalence, only a functional equivalence
result.
As @dick_freebird says, you can do polygon comparison with some scripts. DRC check would be one of them. You could also build your own tcl/skill script to compare each rectangle paint of one design against another design. Think of it as "moving" the mouse automatically to each polygon and checking if the polygon exists in both designs at the same coordinates. I did a bunch of those scripts for short-circuit detection, but I used a little-known GDS tool named: Micromagic. But it is definitely possible to do this in virtuoso too.
For functional comparison, you would perfrom LVS and compare to a golden or schematic netlist. @dick_freebird mentioned Assura, but there are anothe programs like Mentor Graphics Calibre, etc.
For performance comparison, you want to extract the netlist and run spice simulations. that will tell you what the differences are in timing due to parasitic capacitances and resistances.
Not Cadence - but...
"klayout" layout editor provides a functionality to perform XOR and other layout operations on GDS (and not only) layouts and layers.
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