PrimeTime & Design Compiler

What is the difference between Timing analysis done in Design Compiler , Prime Time and ICC Compiler. Which tool is preferred ?

How do we fix setup & hold violations using Design Compiler ?

Post Synthesis (library.db and gatenetlist.v are given as I/P to primetime)- How do we fix setup & hold violations using Prime Time ?

Post PNR (library.db , gatenetlist.v , PNR result are given as I/P to primetime) - How do we fix setup & hold violations using Prime Time ?

PNR - placement & routing

DC, PT, and ICC are only tools that process your design, and tell you "hey, there is timing voilation!". They are not at all responsible for fixing the problem.
Imagine PT as a Fire alarm. It maybe smart enough to call 911, but it is fire fighters to quench the fire!

Primetime does better timing analysis. It is an STA tool.
DC is a synthesis tool while ICC is a PNR tool. So always consider timing results from primetime rather than DC or ICC.

All tools can do timing depending on the input given to the tool. DC considers delays specified directly from constraints. It can even account for wire delays specified through WLM. The delays during DC stage of the flow are more of an approximation. Usually setup is fixed with DC as the clocks are considered ideal. To fix setup you can group paths or try harder for datapath extraction or even try to ungroup cells.

CTS would be done during APR, post which you would have better idea of delays involved in the design as you would be extracting parasitic elements to generate a SPEF. Hold time is fixed during CTS.
PT is used as a sign off tool which is rather pessimistic in its timing. PT always considers worst delays while timing and it can be run post synthesis or post APR. Post APR delays are more realistic so engineers usually run PT here to ensure everything is good with the ckt. PT can fix both setup and hold by buffering different paths and upsizing cells.
The nice thing about timing fixes from PT is that you can write out a script for changes in the design for ICC.

Essentially, all three tools perform timing in very similar manner. The difference being the accuracy of delays avaialbe when these tools are run. You could use a SPEF from a previous ICC run to improve DC's delay optimisation during design re-synthesis as well. It really depends on the flow you use. DC is used for synthesis and ICC is used for APR and parasitic extraction and PT is used for timing sign off.
I would prefer PT for timing and to fix specific paths.