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question about cadence schematic composer?

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nlplable

I am trying to draw an inverter chain using the cadence schematic composer. And at each node it will have 3 inverters parallel(fanout=3 for each inverter). I heard there is a parameter m. If we set the m=3, then we don't need to draw three inverters. How to do this in composer?
Also I draw the schematic in two hierarchy. I defined the inverter symbol by drawing a pmos and nmos at transistor level. I can define the pmos and nmos width(w) and length(l) at transitor level. But how let w and l also show at the inverter chain schematic?
For both of the two questios, should I edit the property of the inverter one by one and add m, w, l and the value for them in order to display all of them?
 

cadence inherited cdf parameters

If I understand well your first question you can do it in the following way:
Open the edit Object Properties of the symbol of the inverter. In the field Instance Name you usually have something like Ixx. Type instead Ixx<0:2> for 3 inverters in parallel.
 

l multiplier cadence

in ---inv---inv---inv--- out
inv inv inv
inv inv inv

I mean like this(don't know how to draw the picture). In this inverter chain, every inverter has fanout=3(all of the inverter has same size). But two of the inverter is just floating. But when you draw the circuit in the composer, you only draw the top ones, set the inveter a parameter m=3(means total three same inverter here and loading is 3). My question is how to set the parameter m?



sutapanaki said:
If I understand well your first question you can do it in the following way:
Open the edit Object Properties of the symbol of the inverter. In the field Instance Name you usually have something like Ixx. Type instead Ixx<0:2> for 3 inverters in parallel.
Click to expand...

Added after 3 minutes:

in ----inv----inv----inv---- out
-------inv---inv-----inv
-------inv---inv-----inv

don't know how to draw it, just ignore the dash line at the two bottom row(They are for alignment purpose).
 

adding cadence width parameter

use I<1:3> as instance names, add wire name for wide wire
 

cadence composer parameterize instances

type 'i', the object property window pop up, in the 'multiplier' box, type in the number you want, for example, you want W=15u, then type in 5 in 'multiplier' box and type in 3 in width box. It possiblly depend on how your candence enviroment is set up.
 

pcell cdf ppar

Well, just add the property "m" to the instances. In analog artist, the hierarchy netlister can recognize the "m" parameter. But the flat mode not.
Another way is to add a CDF parameter "mul" for the inverter. Then set the "Multiplier" of nmos and pmos in the inverter to 'pPar("mul"). To display the parameter "mul", add a "NLPLabel" label "[@mul]" for the inverter's symbol.
 

wire two instances by name cadence

what is "i"? Is it is property of the instance? And what is multiplier box?
tia_design said:
type 'i', the object property window pop up, in the 'multiplier' box, type in the number you want, for example, you want W=15u, then type in 5 in 'multiplier' box and type in 3 in width box. It possiblly depend on how your candence enviroment is set up.
Click to expand...

Added after 13 minutes:

sorry, can't catch it. can you tell me step by step how to do it?
Hughes said:
Well, just add the property "m" to the instances. In analog artist, the hierarchy netlister can recognize the "m" parameter. But the flat mode not.
Another way is to add a CDF parameter "mul" for the inverter. Then set the "Multiplier" of nmos and pmos in the inverter to 'pPar("mul"). To display the parameter "mul", add a "NLPLabel" label "[@mul]" for the inverter's symbol.
Click to expand...

Added after 4 minutes:

can you tell me step by step how to do it, so that I can tell if the circuit I want?
flushrat said:
use I<1:3> as instance names, add wire name for wide wire
Click to expand...
 

cadence edit object parameter

Usually, m parameter is suitable for transistor level but not gate level. m=2 means two times wider as default width. Please think about it . Maybe it will bring troubles if m parameter set to instance !
 

cadence cdf parameter effective

Nugget said:
Usually, m parameter is suitable for transistor level but not gate level. m=2 means two times wider as default width. Please think about it . Maybe it will bring troubles if m parameter set to instance !
Click to expand...

Yes, it will bring troubles if m parameter set to instance!
If set the gate's m parameter (must be named as 'm') to 2, the simulation results will differ between hierarchy netlist mode and flat netlist mode in Analog Artist Environment.
 

cadence schematic label array

how can you display the pmos and nmos size on on this level? and what's the other two pads D and S?
BTW, i don't think this is what i want. I need the three inverter in parallel, but two of the inverters' outputs are floating.
flushrat said:
use I<1:3> as instance names, add wire name for wide wire
Click to expand...
 

composer schematic label

You can also when adding the instance use array m,n numbers to specify the count you want in 2D, in your case, let m=3 and n=3.
 

instance array + cadence

I think u don't need to make 3 inverter in parallel. The reason that it's difficult and area non effective for layout designer make layout of such inverter combination and the capacitances of drain/source areas don't calculated property. If u want u'll can make inverter schematic with inherited pmos and nmos transistor parameters Wp,Lp,Mp,Wn,Ln,Mn, set them like ppar("mul"). Than set them in CDF. And for layout engineer make situable pcell. But I think it's a long way, for custom gates i prefer to have set of cells with different sizes.
 

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